Issued Patents 2017
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9620497 | Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers | Robert J. Gauthier, Jr., Nathan Jack, Junjun Li, Souvick Mitra | 2017-04-11 |
| 9575115 | Methodology of grading reliability and performance of chips across wafer | Nathaniel R. Chadwick, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra +2 more | 2017-02-21 |
| 9536870 | SCR with fin body regions for ESD protection | Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra, Christopher S. Putnam | 2017-01-03 |