Issued Patents 2017
Showing 26–50 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9720725 | Prefetching of discontiguous storage locations as part of transactional execution | Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Valentina Salapura +1 more | 2017-08-01 |
| 9715385 | Vector exception code | Jonathan D. Bradbury, Michael K. Gschwind, Timothy J. Slegel | 2017-07-25 |
| 9715383 | Vector find element equal instruction | Jonathan D. Bradbury, Michael K. Gschwind, Timothy J. Slegel | 2017-07-25 |
| 9710278 | Optimizing grouping of instructions | Fadi Y. Busaba, Michael T. Huffer, David S. Hutton, Edward T. Malley, John G. Rell, Jr. +1 more | 2017-07-18 |
| 9710271 | Collecting transactional execution characteristics during transactional execution | Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Michael K. Gschwind, Valentina Salapura +1 more | 2017-07-18 |
| 9710267 | Instruction to compute the distance to a specified memory boundary | Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Timothy J. Slegel | 2017-07-18 |
| 9710281 | Register comparison for operand store compare (OSC) prediction | David S. Hutton, Wen H. Li | 2017-07-18 |
| 9710266 | Instruction to compute the distance to a specified memory boundary | Jonathan D. Bradbury, Michael K. Gschwind, Christian Jacobi, Timothy J. Slegel | 2017-07-18 |
| 9703718 | Managing read tags in a transactional memory | Dan F. Greiner, Michael K. Gschwind, Chung-Lung K. Shum, Timothy J. Slegel | 2017-07-11 |
| 9703560 | Collecting transactional execution characteristics during transactional execution | Fadi Y. Busaba, Harold W. Cain, III, Dan F. Greiner, Michael K. Gschwind, Valentina Salapura +1 more | 2017-07-11 |
| 9690580 | Decomposition of decimal floating point data | Shawn D. Lundvall, Ronald M. Smith, Sr., Phil C. Yeh | 2017-06-27 |
| 9690623 | Regulating hardware speculative processing around a transaction | Fadi Y. Busaba, Michael K. Gschwind, Chung-Lung K. Shum | 2017-06-27 |
| 9684537 | Regulating hardware speculative processing around a transaction | Fadi Y. Busaba, Michael K. Gschwind, Chung-Lung K. Shum | 2017-06-20 |
| 9658961 | Speculation control for improving transaction success rate, and instruction therefor | Michael K. Gschwind, Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel | 2017-05-23 |
| 9645879 | Salvaging hardware transactions with instructions | Fadi Y. Busaba, Michael K. Gschwind, Maged M. Michael, Valentina Salapura | 2017-05-09 |
| 9639415 | Salvaging hardware transactions with instructions | Fadi Y. Busaba, Michael K. Gschwind, Maged M. Michael, Valentina Salapura | 2017-05-02 |
| 9632820 | Prefetching of discontiguous storage locations in anticipation of transactional execution | Fadi Y. Busaba, Dan F. Greiner, Michael K. Gschwind, Maged M. Michael, Valentina Salapura +1 more | 2017-04-25 |
| 9619383 | Dynamic predictor for coalescing memory transactions | Fadi Y. Busaba, Harold W. Cain, III, Michael K. Gschwind, Maged M. Michael | 2017-04-11 |
| 9594561 | Instruction stream tracing of multi-threaded processors | Lee Evan Eisen, Lisa C. Heller, Michael T. Huffer | 2017-03-14 |
| 9588762 | Vector find element not equal instruction | Jonathan D. Bradbury, Michael K. Gschwind, Timothy J. Slegel | 2017-03-07 |
| 9588763 | Vector find element not equal instruction | Jonathan D. Bradbury, Michael K. Gschwind, Timothy J. Slegel | 2017-03-07 |
| 9575890 | Supporting atomic accumulation with an addressable accumulator | Fadi Y. Busaba, Michael K. Gschwind | 2017-02-21 |
| 9563468 | Interprocessor memory status communication | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel | 2017-02-07 |
| 9563467 | Interprocessor memory status communication | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum, Timothy J. Slegel | 2017-02-07 |
| 9535696 | Instruction to cancel outstanding cache prefetches | Michael K. Gschwind, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum | 2017-01-03 |