Issued Patents 2017
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9812543 | Common metal contact regions having different Schottky barrier heights and methods of manufacturing same | Tek Po Rinus Lee, Ruilong Xie | 2017-11-07 |
| 9805982 | Apparatus and method of adjusting work-function metal thickness to provide variable threshold voltages in finFETs | Hui Zang, Min-hwa Chi | 2017-10-31 |
| 9773680 | Advanced method for scaled SRAM with flexible active pitch | Hui Zang | 2017-09-26 |
| 9761452 | Devices and methods of forming SADP on SRAM and SAQP on logic | Jiehui Shu, Daniel Jaeger, Garo Derderian, Haifeng Sheng | 2017-09-12 |
| 9754837 | Controlling within-die uniformity using doped polishing material | Haigou Huang, Huang Liu, Taifong Chao | 2017-09-05 |
| 9711447 | Self-aligned lithographic patterning with variable spacings | Jiehui Shu, Qiang Fang, Daniel W. Fisher, Haigou Huang, Haifeng Sheng +1 more | 2017-07-18 |
| 9704746 | Advanced self-aligned patterning process with sit spacer as a final dielectric etch hardmask | Jiehui Shu, Archana Subramaniyan | 2017-07-11 |
| 9698018 | Introducing self-aligned dopants in semiconductor fins | Xintuo Dai, Haigou Huang | 2017-07-04 |
| 9673301 | Methods of forming spacers on FinFET devices | Fuad H. Al-Amoody, Haifeng Sheng | 2017-06-06 |
| 9640423 | Integrated circuits and methods for their fabrication | Bharat Krishnan, Shishir Ray | 2017-05-02 |
| 9627274 | Methods of forming self-aligned contacts on FinFET devices | Haifeng Sheng, Xintuo Dai, Huang Liu | 2017-04-18 |
| 9620425 | Method of adjusting spacer thickness to provide variable threshold voltages in FinFETs | Hui Zang, Min-hwa Chi | 2017-04-11 |
| 9589807 | Method for eliminating interlayer dielectric dishing and controlling gate height uniformity | Haigou Huang, Huang Liu, Yuanfang Lu | 2017-03-07 |
| 9577066 | Methods of forming fins with different fin heights | Fuad H. Al-Amoody | 2017-02-21 |
| 9570552 | Forming symmetrical stress liners for strained CMOS vertical nanowire field-effect transistors | Tek Po Rinus Lee | 2017-02-14 |
| 9553194 | Method for improved fin profile | Nicholas V. LiCausi, Zhenyu Hu, Hong Yu | 2017-01-24 |