Issued Patents 2016
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9517539 | Wafer susceptor with improved thermal characteristics | Yi-Hung Lin, Jr-Hung Li, Chang-Shen Lu, Tze-Liang Lee | 2016-12-13 |
| 9484265 | Structure and method for semiconductor device | Yi-Jing Lee, Kun-Mu Li, Tze-Liang Lee | 2016-11-01 |
| 9425287 | Reducing variation by using combination epitaxy growth | Yu-Hung Cheng, Yi-Hung Lin, Tze-Liang Lee | 2016-08-23 |
| 9412868 | Semiconductor device and fabrication method thereof | Yen-Ru Lee, Ming-Hua Yu, Tze-Liang Lee, Pang-Yen Tsai, Lilly Su +2 more | 2016-08-09 |
| 9401426 | Semiconductor device and fabrication method thereof | Lilly Su, Pang-Yen Tsai, Tze-Liang Lee, Yen-Ru Lee, Ming-Hua Yu | 2016-07-26 |
| 9362360 | Modulating germanium percentage in MOS devices | Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Tze-Liang Lee | 2016-06-07 |
| 9356136 | Engineered source/drain region for n-Type MOSFET | Wei-Yuan Lu, Lilly Su, Chun-Hung Huang, Jyh-Huei Chen | 2016-05-31 |
| 9337337 | MOS device having source and drain regions with embedded germanium-containing diffusion barrier | Tsz-Mei Kwok, Kun-Mu Li, Hsueh-Chang Sung, Tze-Liang Lee | 2016-05-10 |
| 9287398 | Transistor strain-inducing scheme | Tsz-Mei Kwok, Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee | 2016-03-15 |
| 9287382 | Structure and method for semiconductor device | Yi-Jing Lee, Kun-Mu Li, Tze-Liang Lee | 2016-03-15 |
| 9281196 | Method to reduce etch variation using ion implantation | Tsan-Chun Wang, Ziwei Fang, Tze-Liang Lee, Chao-Cheng Chen, Syun-Ming Jang | 2016-03-08 |
| 9269777 | Source/drain structures and methods of forming same | Yi-Jing Lee, Kun-Mu Li, Tze-Liang Lee | 2016-02-23 |
| 9263339 | Selective etching in the formation of epitaxy regions in MOS devices | Yu-Hung Cheng, Tze-Liang Lee | 2016-02-16 |