Issued Patents 2016
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9515148 | Bridging local semiconductor interconnects | Chieh-Yu Lin, Yannick Daurelle | 2016-12-06 |
| 9472463 | Patterning process for Fin implantation | Huihang Dong | 2016-10-18 |
| 9465290 | Near-infrared absorbing film compositions | Wu-Song Huang, Martin Glodde, Dario L. Goldfarb, Sen Liu, Libor Vyklicky | 2016-10-11 |
| 9449822 | Method of forming semiconductor structures with contact holes | Wu-Song Huang, Joy Cheng, Kuang-Jung Chen | 2016-09-20 |
| 9443770 | Patterning process for fin implantation | Huihang Dong | 2016-09-13 |
| 9391014 | Physical unclonable interconnect function array | Kai D. Feng, Ping-Chuan Wang, Zhijian Yang | 2016-07-12 |
| 9391030 | On-chip semiconductor device having enhanced variability | Chengwen Pei, Ping-Chuan Wang | 2016-07-12 |
| 9337261 | Method of forming microelectronic or micromechanical structures | Samuel S. Choi | 2016-05-10 |
| 9337082 | Metal lines having etch-bias independent height | Junjing Bao | 2016-05-10 |
| 9331012 | Method for fabricating a physical unclonable interconnect function array | Kai D. Feng, Ping-Chuan Wang, Zhijian Yang | 2016-05-03 |
| 9316916 | Method to mitigate resist pattern critical dimension variation in a double-exposure process | Kuang-Jung Chen, Wu-Song Huang | 2016-04-19 |
| 9312366 | Processing of integrated circuit for metal gate replacement | Huihang Dong | 2016-04-12 |
| 9312191 | Block patterning process for post fin | — | 2016-04-12 |
| 9281236 | Embedded on-chip security | Kai D. Feng, Ping-Chuan Wang, Zhijian Yang | 2016-03-08 |
| 9240376 | Self-aligned via fuse | Junjing Bao, Samuel S. Choi | 2016-01-19 |
| 9236575 | Dynamic alignment by electrical potential and flow control to single-wall carbon nanotube field effect transistors | Hanfei Wang | 2016-01-12 |