Issued Patents 2016
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9520876 | Power gating and clock gating in wiring levels | Tassbieh Hassan, Kirk D. Peterson, John E. Sheets, II, Christine Whiteside | 2016-12-13 |
| 9472269 | Stress balancing of circuits | Igor Arsovski, John Bradley Deforge, Ezra D. B. Hall, Kirk D. Peterson | 2016-10-18 |
| 9437670 | Light activated test connections | John Bradley Deforge, John J. Ellis-Monaghan, Jeffrey P. Gambino, Ezra D. B. Hall, Marc D. Knox +1 more | 2016-09-06 |
| 9383767 | Circuit design for balanced logic stress | Frances S. M. Clougherty, William Paul Hovis, Kirk D. Peterson, Mack W. Riley | 2016-07-05 |
| 9250645 | Circuit design for balanced logic stress | Frances S. M. Clougherty, William Paul Hovis, Kirk D. Peterson, Mack W. Riley | 2016-02-02 |