Issued Patents 2016
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9530785 | Three-dimensional memory devices having a single layer channel and methods of making thereof | Sateesh Koka, Zhenyu Lu, Wei Zhao, Henry Chien, Yingda Dong +6 more | 2016-12-27 |
| 9520146 | Method of forming a fully wrapped-around shielded PMR writer pole | Jinwen Wang, Weimin Si, Jianxin Fang, Ying Hong, Hongzhou Jiang +5 more | 2016-12-13 |
| 9443861 | Fluorine-blocking insulating spacer for backside contact structure of three-dimensional memory structures | Jayavel Pachamuthu, Johann Alsmeier | 2016-09-13 |
| 9437470 | Self-aligned trench isolation in integrated circuits | Lei Xue, Kenichi Ohtsuka, Simon S. Chan, Rinji Sugino | 2016-09-06 |
| 9437305 | Programming memory with reduced short-term charge loss | Yingda Dong, Liang Pang, Tien-Chien Kuo | 2016-09-06 |
| 9406387 | Charge redistribution during erase in charge trapping memory | Jiahui Yuan, Yingda Dong | 2016-08-02 |
| 9378832 | Method to recover cycling damage and improve long term data retention | Zhengyi Zhang, Wei Zhao, Yingda Dong, Jian Chen | 2016-06-28 |
| 9324439 | Weak erase after programming to improve data retention in charge-trapping memory | Hong-Yan Chen, Yingda Dong | 2016-04-26 |
| 9312010 | Programming of drain side word line to reduce program disturb and charge loss | Jiahui Yuan, Yingda Dong, Wei Zhao | 2016-04-12 |
| 9257191 | Charge redistribution during erase in charge trapping memory | Jiahui Yuan, Yingda Dong | 2016-02-09 |
| 9252154 | Non-volatile memory with silicided bit line contacts | Simon S. Chan, Hidehiko Shiraiwa, Lei Xue | 2016-02-02 |
| 9252026 | Buried trench isolation in integrated circuits | Rinji Sugino, Lei Xue, Simon S. Chan | 2016-02-02 |
| 9230663 | Programming memory with reduced short-term charge loss | Yingda Dong, Liang Pang, Tien-Chien Kuo | 2016-01-05 |