| 9490364 |
Semiconductor transistor having a stressed channel |
Robert S. Chau, Tahir Ghani, Kaizad Mistry |
2016-11-08 |
| 9484432 |
Contact resistance reduction employing germanium overlayer pre-contact metalization |
Glenn A. Glass, Tahir Ghani |
2016-11-01 |
| 9484447 |
Integration methods to fabricate internal spacers for nanowire devices |
Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Mark Armstrong, Rafael Rios +2 more |
2016-11-01 |
| 9437691 |
Column IV transistors for PMOS integration |
Glenn A. Glass |
2016-09-06 |
| 9437710 |
Method for improving transistor performance through reducing the salicide interface resistance |
Boyan Boyanov, Glenn A. Glass, Thomas Hoffman |
2016-09-06 |
| 9397102 |
III-V layers for N-type and P-type MOS source-drain contacts |
Glenn A. Glass, Tahir Ghani |
2016-07-19 |
| 9385221 |
Nanowire transistor with underlayer etch stops |
Seiyon Kim, Daniel B. Aubertine, Kelin J. Kuhn |
2016-07-05 |
| 9349810 |
Selective germanium P-contact metalization through trench |
Glenn A. Glass, Tahir Ghani |
2016-05-24 |
| 9343559 |
Nanowire transistor devices and forming techniques |
Glenn A. Glass, Kelin J. Kuhn, Seiyon Kim, Daniel B. Aubertine |
2016-05-17 |
| 9231076 |
Enhanced dislocation stress transistor |
Cory E. Weber, Mark Liu, Hemant Deshpande, Daniel B. Aubertine |
2016-01-05 |