Issued Patents 2016
Showing 126–150 of 164 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9311249 | Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer | Anthony J. Bybell, Bradly G. Frey, Benjamin Herrenschmidt, Paul Mackerras | 2016-04-12 |
| 9311095 | Using register last use information to perform decode time computer instruction optimization | Valentina Salapura | 2016-04-12 |
| 9311093 | Prefix computer instruction for compatibly extending instruction functionality | Valentina Salapura | 2016-04-12 |
| 9304935 | Enhancing reliability of transaction execution by using transaction digests | Valentina Salapura | 2016-04-05 |
| 9298464 | Instruction merging optimization | Valentina Salapura | 2016-03-29 |
| 9298626 | Managing high-conflict cache lines in transactional memory computing environments | Fadi Y. Busaba, Harold W. Cain, III, Maged M. Michael, Valentina Salapura, Eric M. Schwarz +1 more | 2016-03-29 |
| 9298623 | Identifying high-conflict cache lines in transactional memory computing environments | Fadi Y. Busaba, Harold W. Cain, III, Maged M. Michael, Valentina Salapura, Eric M. Schwarz +1 more | 2016-03-29 |
| 9298459 | Managing register pairing | Jonathan D. Bradbury | 2016-03-29 |
| 9292289 | Enhancing reliability of transaction execution by using transaction digests | Valentina Salapura | 2016-03-22 |
| 9292444 | Multi-granular cache management in multi-processor computing environments | Fadi Y. Busaba, Harold W. Cain, III, Maged M. Michael, Valentina Salapura, Eric M. Schwarz +1 more | 2016-03-22 |
| 9292357 | Software enabled and disabled coalescing of memory transactions | Fadi Y. Busaba, Valentina Salapura, Chung-Lung K. Shum | 2016-03-22 |
| 9292337 | Software enabled and disabled coalescing of memory transactions | Fadi Y. Busaba, Valentina Salapura, Chung-Lung K. Shum | 2016-03-22 |
| 9292291 | Instruction merging optimization | Valentina Salapura | 2016-03-22 |
| 9286072 | Using register last use infomation to perform decode-time computer instruction optimization | Valentina Salapura | 2016-03-15 |
| 9280333 | Selection of an entry point of a function having multiple entry points | Ulrich Weigand | 2016-03-08 |
| 9280488 | Asymmetric co-existent address translation structure formats | Anthony J. Bybell, David D. Dukro, Bradly G. Frey | 2016-03-08 |
| 9280348 | Decode time instruction optimization for load reserve and store conditional sequences | — | 2016-03-08 |
| 9280347 | Transforming non-contiguous instruction specifiers to contiguous instruction specifiers | — | 2016-03-08 |
| 9274769 | Table of contents pointer value save and restore placeholder positioning | Ulrich Weigand | 2016-03-01 |
| 9268572 | Modify and execute next sequential instruction facility and instructions therefor | Eric M. Schwarz | 2016-02-23 |
| 9268566 | Character data match determination by loading registers at most up to memory block boundary and comparing | Jonathan D. Bradbury, Timothy J. Slegel | 2016-02-23 |
| 9262343 | Transactional processing based upon run-time conditions | Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum | 2016-02-16 |
| 9262161 | Tracking multiple conditions in a general purpose register and instruction therefor | Dan F. Greiner | 2016-02-16 |
| 9256546 | Transparent code patching including updating of address translation structures | — | 2016-02-09 |
| 9256550 | Hybrid address translation | Anthony J. Bybell | 2016-02-09 |