Issued Patents 2016
Showing 101–125 of 164 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9354874 | Scalable decode-time instruction sequence optimization of dependent instructions | Valentina Salapura | 2016-05-31 |
| 9348522 | Software indications and hints for coalescing memory transactions | Fadi Y. Busaba, Valentina Salapura, Chung-Lung K. Shum | 2016-05-24 |
| 9348763 | Asymmetric co-existent address translation structure formats | Anthony J. Bybell, David D. Dukro, Bradly G. Frey | 2016-05-24 |
| 9348757 | System supporting multiple partitions with differing translation formats | — | 2016-05-24 |
| 9348643 | Prefetching of discontiguous storage locations as part of transactional execution | Fadi Y. Busaba, Dan F. Greiner, Maged M. Michael, Valentina Salapura, Eric M. Schwarz +1 more | 2016-05-24 |
| 9348616 | Linking a function with dual entry points | Ulrich Weigand | 2016-05-24 |
| 9348596 | Forming instruction groups based on decode time instruction optimization | — | 2016-05-24 |
| 9348523 | Code optimization to enable and disable coalescing of memory transactions | Fadi Y. Busaba, Maged M. Michael, Valentina Salapura, Chung-Lung K. Shum | 2016-05-24 |
| 9342337 | Privilege level aware processor hardware resource management facility | Giles R. Frazier, Naresh Nayar | 2016-05-17 |
| 9336097 | Salvaging hardware transactions | Harold W. Cain, III, Maged M. Michael, Valentina Salapura, Eric M. Schwarz | 2016-05-10 |
| 9336047 | Prefetching of discontiguous storage locations in anticipation of transactional execution | Fadi Y. Busaba, Dan F. Greiner, Maged M. Michael, Valentina Salapura, Eric M. Schwarz +1 more | 2016-05-10 |
| 9329868 | Reducing register read ports for register pairs | Jonathan D. Bradbury | 2016-05-03 |
| 9330023 | Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces | Anthony J. Bybell, Bradly G. Frey, Benjamin Herrenschmidt, Paul Mackerras | 2016-05-03 |
| 9329946 | Salvaging hardware transactions | Harold W. Cain, III, Maged M. Michael, Valentina Salapura, Eric M. Schwarz | 2016-05-03 |
| 9329890 | Managing high-coherence-miss cache lines in multi-processor computing environments | Fadi Y. Busaba, Harold W. Cain, III, Maged M. Michael, Valentina Salapura, Eric M. Schwarz +1 more | 2016-05-03 |
| 9329875 | Global entry point and local entry point for callee function | Ulrich Weigand | 2016-05-03 |
| 9329869 | Prefix computer instruction for compatibily extending instruction functionality | Valentina Salapura | 2016-05-03 |
| 9329850 | Relocation of instructions that use relative addressing | Valentina Salapura | 2016-05-03 |
| 9323530 | Caching optimized internal instructions in loop buffer | Valentina Salapura | 2016-04-26 |
| 9323692 | Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer | Anthony J. Bybell, Bradly G. Frey, Benjamin Herrenschmidt, Paul Mackerras | 2016-04-26 |
| 9323568 | Indicating a low priority transaction | Fadi Y. Busaba, Eric M. Schwarz | 2016-04-26 |
| 9323532 | Predicting register pairs | Jonathan D. Bradbury | 2016-04-26 |
| 9323529 | Reducing register read ports for register pairs | Jonathan D. Bradbury | 2016-04-26 |
| 9317443 | Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces | Anthony J. Bybell, Bradly G. Frey, Benjamin Herrenschmidt, Paul Mackerras | 2016-04-19 |
| 9317379 | Using transactional execution for reliability and recovery of transient failures | Valentina Salapura | 2016-04-19 |