| 9430166 |
Interaction of transactional storage accesses with other atomic semantics |
Guy L. Guthrie, Cathy May, Derek E. Williams |
2016-08-30 |
| 9396115 |
Rewind only transactions in a data processing system supporting transactional storage accesses |
Robert J. Blainey, Guy L. Guthrie, Cathy May, Derek E. Williams |
2016-07-19 |
| 9367264 |
Transaction check instruction for memory transactions |
Guy L. Guthrie, Cathy May, Derek E. Williams |
2016-06-14 |
| 9367263 |
Transaction check instruction for memory transactions |
Guy L. Guthrie, Cathy May, Derek E. Williams |
2016-06-14 |
| 9348763 |
Asymmetric co-existent address translation structure formats |
Anthony J. Bybell, David D. Dukro, Michael K. Gschwind |
2016-05-24 |
| 9342454 |
Nested rewind only and non rewind only transactions in a data processing system supporting transactional storage accesses |
Guy L. Guthrie, Cathy May, Derek E. Williams |
2016-05-17 |
| 9330023 |
Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces |
Anthony J. Bybell, Michael K. Gschwind, Benjamin Herrenschmidt, Paul Mackerras |
2016-05-03 |
| 9323692 |
Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer |
Anthony J. Bybell, Michael K. Gschwind, Benjamin Herrenschmidt, Paul Mackerras |
2016-04-26 |
| 9317443 |
Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces |
Anthony J. Bybell, Michael K. Gschwind, Benjamin Herrenschmidt, Paul Mackerras |
2016-04-19 |
| 9311249 |
Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer |
Anthony J. Bybell, Michael K. Gschwind, Benjamin Herrenschmidt, Paul Mackerras |
2016-04-12 |
| 9280488 |
Asymmetric co-existent address translation structure formats |
Anthony J. Bybell, David D. Dukro, Michael K. Gschwind |
2016-03-08 |
| 9268598 |
Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories |
Robert J. Blainey, Harold W. Cain, III, Susan E. Eisen, Charles B. Hall, Hung Q. Le +1 more |
2016-02-23 |
| 9251088 |
Mechanisms for eliminating a race condition between a hypervisor-performed emulation process requiring a translation operation and a concurrent translation table entry invalidation |
Michael K. Gschwind, Benjamin Herrenschmidt |
2016-02-02 |
| 9244846 |
Ensuring causality of transactional storage accesses interacting with non-transactional storage accesses |
Cathy May, Derek E. Williams |
2016-01-26 |
