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Split-level history buffer in a computer processing unit |
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2016-12-20 |
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Techniques for increasing vector processing utilization and efficiency through vector lane predication prediction |
Jose E. Moreira, Pratap C. Pattnaik, Brian W. Thompto, Jessica Hui-Chun Tseng |
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Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories |
Robert J. Blainey, Harold W. Cain, III, Susan E. Eisen, Bradly G. Frey, Charles B. Hall +1 more |
2016-02-23 |
| 9268599 |
Recording and profiling transaction failure addresses of the abort-causing and approximate abort-causing data and instructions in hardware transactional memories |
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2016-02-23 |
