Issued Patents 2016
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9531406 | Decoding of LDPC code | Evangelos S. Eleftheriou, Robert Haas, Xiao-Yu Hu | 2016-12-27 |
| 9524171 | Split-level history buffer in a computer processing unit | Hung Q. Le, David R. Terry | 2016-12-20 |
| 9489207 | Processor and method for partially flushing a dispatched instruction group including a mispredicted branch | William E. Burky, Brian R. Mestan, Balaram Sinharoy, Benjamin W. Stolt | 2016-11-08 |
| 9389870 | Age based fast instruction issue | Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney | 2016-07-12 |
| 9389867 | Speculative finish of instruction execution in a processor core | Sundeep Chadha, Bryan Lloyd, David Scott Ray, Benjamin W. Stolt | 2016-07-12 |
| 9384002 | Speculative finish of instruction execution in a processor core | Sundeep Chadha, Bryan Lloyd, David Scott Ray, Benjamin W. Stolt | 2016-07-05 |
| 9367322 | Age based fast instruction issue | Jeffrey C. Brownscheidle, Sundeep Chadha, Maureen A. Delaney | 2016-06-14 |
| 9286068 | Efficient usage of a multi-level register file utilizing a register file bypass | Christopher M. Abernathy, Mary D. Brown, Sundeep Chadha | 2016-03-15 |