Issued Patents 2016
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9530691 | Methods, apparatus and system for forming a dielectric field for dual orientation self aligned vias | Errol Todd Ryan | 2016-12-27 |
| 9466530 | Methods of forming an improved via to contact interface by selective formation of a metal silicide capping layer | Tibor Bolom, Errol Todd Ryan | 2016-10-11 |
| 9437711 | Methods of forming gate structures for semiconductor devices using a replacement gate technique and the resulting devices | Xiuyu Cai | 2016-09-06 |
| 9425280 | Semiconductor device with low-K spacers | Xiuyu Cai, Ruilong Xie | 2016-08-23 |
| 9412660 | Methods of forming V0 structures for semiconductor devices that includes recessing a contact structure | Ruilong Xie | 2016-08-09 |
| 9391140 | Raised fin structures and methods of fabrication | Yi Qi, Catherine B. Labelle | 2016-07-12 |
| 9373542 | Integrated circuits and methods for fabricating integrated circuits with improved contact structures | Xiuyu Cai, Hoon Kim | 2016-06-21 |
| 9343406 | Device having self-repair Cu barrier for solving barrier degradation due to Ru CMP | Kunaljeet Tanwar | 2016-05-17 |
| 9318436 | Copper based nitride liner passivation layers for conductive copper structures | Larry Zhao, Ming He, Sean Xuan Lin, John A. Iacoponi, Errol Todd Ryan | 2016-04-19 |
| 9299745 | Integrated circuits having magnetic tunnel junctions (MTJ) and methods for fabricating the same | Sean Xuan Lin, Kunaljeet Tanwar | 2016-03-29 |
| 9297775 | Combinatorial screening of metallic diffusion barriers | Edwin Adhiprakasha, Sean Barstow, Ashish Bodke, Zhendong Hong, Usha Raghuram +3 more | 2016-03-29 |
| 9287213 | Integrated circuits with improved contact structures | Xuan Lin, Vimal Kamineni | 2016-03-15 |
| 9275874 | Methods for fabricating integrated circuits using chemical mechanical planarization to recess metal | Kunaljeet Tanwar, Donald F. Canaperi, Raghuveer R. Patlolla | 2016-03-01 |
| 9269615 | Multi-layer barrier layer for interconnect structure | Vivian W. Ryan, Paul R. Besser | 2016-02-23 |
| 9263327 | Minimizing void formation in semiconductor vias and trenches | Sean Xuan Lin | 2016-02-16 |
| 9236557 | Magnetic tunnel junction between metal layers of a semiconductor device | Ruilong Xie, Xiuyu Cai, Hyun-Jin Cho | 2016-01-12 |
| 9236299 | Methods of forming a metal cap layer on copper-based conductive structures on an integrated circuit device | Hoon Kim, Christian Witt, Larry Zhao | 2016-01-12 |