AL

Albert Y. Lee

CS Cadence Design Systems: 1 patents #62 of 259Top 25%
📍 Livermore, CA: #77 of 244 inventorsTop 35%
🗺 California: #14,783 of 41,698 inventorsTop 40%
Overall (2011): #357,796 of 364,097Top 100%
1
Patents 2011

Issued Patents 2011

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
7886238 Visual yield analysis of intergrated circuit layouts Harsh Sharma, Rajeev Srivastava, Srinivas R. Kommoori, Bharat Bhushan, Mithunjoy Parui 2011-02-08