RS

Rajeev Srivastava

CS Cadence Design Systems: 1 patents #62 of 259Top 25%
🗺 Texas: #3,688 of 11,512 inventorsTop 35%
Overall (2011): #188,397 of 364,097Top 55%
1
Patents 2011

Issued Patents 2011

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
7886238 Visual yield analysis of intergrated circuit layouts Harsh Sharma, Srinivas R. Kommoori, Bharat Bhushan, Mithunjoy Parui, Albert Y. Lee 2011-02-08