HS

Harsh Sharma

CS Cadence Design Systems: 1 patents #62 of 259Top 25%
📍 New Delhi, NJ: #1 of 1 inventorsTop 100%
Overall (2011): #290,675 of 364,097Top 80%
1
Patents 2011

Issued Patents 2011

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
7886238 Visual yield analysis of intergrated circuit layouts Rajeev Srivastava, Srinivas R. Kommoori, Bharat Bhushan, Mithunjoy Parui, Albert Y. Lee 2011-02-08