Issued Patents 2011
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8051352 | Timing-aware test generation and fault simulation | Xijiang Lin, Kun-Han Tsai, Chen Wang, Janusz Rajski | 2011-11-01 |
| 8024387 | Method for synthesizing linear finite state machines | Janusz Rajski, Jerzy Tyszer, Nilanjan Mukherjee | 2011-09-20 |
| 7984354 | Generating responses to patterns stimulating an electronic circuit with timing exception paths | Dhiraj Goswami, Kun-Han Tsai, Janusz Rajski | 2011-07-19 |
| 7925465 | Low power scan testing techniques and apparatus | Xijiang Lin, Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer | 2011-04-12 |
| 7900104 | Test pattern compression for an integrated circuit test environment | Janusz Rajski, Nilanjan Mukherjee, Jerzy Tyszer | 2011-03-01 |
| 7877656 | Continuous application and decompression of test patterns to a circuit-under-test | Janusz Rajski, Nilanjan Mukherjee, Jerzy Tyszer | 2011-01-25 |
| 7865794 | Decompressor/PRPG for applying pseudo-random and deterministic test patterns | Janusz Rajski, Jerzy Tyszer, Nilanjan Mukherjee | 2011-01-04 |