Issued Patents 2005
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6893962 | Low via resistance system | Prabhakar P. Tripathi, Weidan Li | 2005-05-17 |
| 6881664 | Process for planarizing upper surface of damascene wiring structure for integrated circuit structures | Wilbur G. Catabay, Richard Schinella, Wei-Jen Hsia | 2005-04-19 |