RS

Richard Schinella

Lsi Logic: 1 patents #164 of 465Top 40%
📍 Saratoga, CA: #143 of 352 inventorsTop 45%
🗺 California: #7,981 of 26,868 inventorsTop 30%
Overall (2005): #115,535 of 245,428Top 50%
1
Patents 2005

Issued Patents 2005

Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
6881664 Process for planarizing upper surface of damascene wiring structure for integrated circuit structures Wilbur G. Catabay, Zhihai Wang, Wei-Jen Hsia 2005-04-19