Issued Patents 2005
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6933188 | Use of a selective hard mask for the integration of double diffused drain MOS devices in deep sub-micron fabrication technologies | Purakh Raj Verma, Hwee Ngoh Chua | 2005-08-23 |
| 6903013 | Method to fill a trench and tunnel by using ALD seed layer and electroless plating | Lap Chan, Chit Hwei Ng, Yong Ju, Jia Zhen Zheng | 2005-06-07 |
| 6869884 | Process to reduce substrate effects by forming channels under inductor devices and around analog blocks | Lap Chan, Chit Hwei Ng, Purakh Raj Verma, Jia Zhen Zheng, Johnny Kok Wai Chew +1 more | 2005-03-22 |
| 6861317 | Method of making direct contact on gate by using dielectric stop layer | Purakh Raj Verma, Lap Chan, Yelehanka Ramachandramurthy Pradeep, Kai Shao, Jia Zhen Zheng | 2005-03-01 |
| 6852605 | Method of forming an inductor with continuous metal deposition | Chit Hwei Ng, Lap Chan, Purakh Raj Verma, Yelehanka Ramachandramurthy Pradeep | 2005-02-08 |