Issued Patents 2005
Showing 1–25 of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6978432 | Method and apparatus for propagating a piecewise linear function to a point | Andrew Caldwell | 2005-12-20 |
| 6976238 | Circular vias and interconnect-line ends | Akira Fujimura, Andrew Caldwell | 2005-12-13 |
| 6976237 | Method and apparatus for estimating distances in a region | Jonathan Frankle | 2005-12-13 |
| 6973634 | IC layouts with at least one layer that has more than one preferred interconnect direction, and method and apparatus for generating such a layout | Andrew Caldwell, Etienne Jacques | 2005-12-06 |
| 6961914 | Method and apparatus for selecting input points to train a machine learning model for extraction | Arindam Chatterjee | 2005-11-01 |
| 6959304 | Method and apparatus for representing multidimensional data | Tom Kronmiller, Andrew Siegel | 2005-10-25 |
| 6957408 | Method and apparatus for routing nets in an integrated circuit layout | Andrew Caldwell, Etienne Jacques | 2005-10-18 |
| 6957410 | Method and apparatus for adaptively selecting the wiring model for a design region | Oscar Buset | 2005-10-18 |
| 6957409 | Method and apparatus for generating topological routes for IC layouts using perturbations | Andrew Caldwell | 2005-10-18 |
| 6957411 | Gridless IC layout and method and apparatus for generating such a layout | Andrew Caldwell, Etienne Jacques | 2005-10-18 |
| 6954910 | Method and apparatus for producing a circuit description of a design | Asmus Hetzel | 2005-10-11 |
| 6952815 | Probabilistic routing method and apparatus | Oscar Buset | 2005-10-04 |
| 6951006 | Decomposing IC regions and embedding routes | Andrew Caldwell | 2005-09-27 |
| 6951005 | Method and apparatus for selecting a route for a net based on the impact on other nets | Andrew Caldwell | 2005-09-27 |
| 6948144 | Method and apparatus for costing a path expansion | Andrew Caldwell | 2005-09-20 |
| 6944841 | Method and apparatus for proportionate costing of vias | Andrew Caldwell | 2005-09-13 |
| 6941531 | Method and apparatus for performing extraction on an integrated circuit design | Arindam Chatterjee | 2005-09-06 |
| 6938234 | Method and apparatus for defining vias | Andrew Caldwell, Etienne Jacques | 2005-08-30 |
| 6931616 | Routing method and apparatus | Oscar Buset, Etienne Jacques | 2005-08-16 |
| 6931615 | Method and apparatus for identifying a path between source and target states | Andrew Caldwell | 2005-08-16 |
| 6931608 | Method and apparatus for determining viability of path expansions | Andrew Caldwell | 2005-08-16 |
| 6928633 | IC layout having topological routes | Andrew Caldwell | 2005-08-09 |
| 6925618 | Method and apparatus for performing extraction on an integrated circuit design with support vector machines | Arindam Chatterjee | 2005-08-02 |
| 6915499 | Method and apparatus for propagating a piecewise linear function to a line | Andrew Caldwell | 2005-07-05 |
| 6915500 | Method and arrangement for layout and manufacture of nonmanhattan semiconductor integrated circuit using simulated Euclidean wiring | Andrew Caldwell | 2005-07-05 |