EJ

Etienne Jacques

CS Cadence Design Systems: 6 patents #4 of 77Top 6%
📍 Bristol, CA: #1 of 10 inventorsTop 10%
Overall (2005): #4,762 of 245,428Top 2%
6
Patents 2005

Issued Patents 2005

Showing 1–6 of 6 patents

Patent #TitleCo-InventorsDate
6973634 IC layouts with at least one layer that has more than one preferred interconnect direction, and method and apparatus for generating such a layout Steven Teig, Andrew Caldwell 2005-12-06
6957408 Method and apparatus for routing nets in an integrated circuit layout Steven Teig, Andrew Caldwell 2005-10-18
6957411 Gridless IC layout and method and apparatus for generating such a layout Steven Teig, Andrew Caldwell 2005-10-18
6938234 Method and apparatus for defining vias Steven Teig, Andrew Caldwell 2005-08-30
6931616 Routing method and apparatus Steven Teig, Oscar Buset 2005-08-16
6892371 Method and apparatus for performing geometric routing Steven Teig 2005-05-10