Issued Patents 2004
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6825096 | Method of forming an alignment mark structure using standard process steps for forming vertical gate transistors | — | 2004-11-30 |
| 6806200 | Method of improving etch uniformity in deep silicon etching | David M. Dobuzinsky, Siddhartha Panda, Richard S. Wise | 2004-10-19 |
| 6797636 | Process of fabricating DRAM cells with collar isolation layers | Helmut Tews | 2004-09-28 |
| 6762443 | Vertical transistor and transistor fabrication method | — | 2004-07-13 |
| 6713884 | Method of forming an alignment mark structure using standard process steps for forming vertical gate transistors | — | 2004-03-30 |