Issued Patents 2004
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6825102 | Method of improving the quality of defective semiconductor material | Stephen W. Bedell, Shreesh Narasimha, Devendra K. Sadana | 2004-11-30 |
| 6805962 | Method of creating high-quality relaxed SiGe-on-insulator for strained Si CMOS applications | Stephen W. Bedell, Jack O. Chu, Steven J. Koester, Devendra K. Sadana, John A. Ott | 2004-10-19 |
| 6803240 | Method of measuring crystal defects in thin Si/SiGe bilayers | Stephen W. Bedell, Devendra K. Sadana | 2004-10-12 |
| 6800518 | Formation of patterned silicon-on-insulator (SOI)/silicon-on-nothing (SON) composite structure by porous Si engineering | Robert E. Bendernagel, Kwang Su Choe, Bijan Davari, Devendra K. Sadana, Ghavam G. Shahidi +1 more | 2004-10-05 |
| 6722032 | Method of forming a structure for electronic devices contact locations | Brian S. Beaman, Paul A. Lauro, Maurice Heathcote Norcott, Da-Yuan Shih | 2004-04-20 |
| 6717217 | Ultimate SIMOX | Maurice Heathcote Norcott, Devendra K. Sadana | 2004-04-06 |
| 6708403 | Angled flying lead wire bonding process | Brian S. Beaman, Paul A. Lauro, Da-Yuan Shih | 2004-03-23 |