Issued Patents 2003
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6637016 | Assignment of cell coordinates | Elyar E. Gasanov, Andrej A. Zolotykh, Aiguo Lu | 2003-10-21 |
| 6629304 | Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cells | Elyar E. Gasanov, Andrej A. Zolotykh, Aiguo Lu | 2003-09-30 |
| 6615397 | Optimal clock timing schedule for an integrated circuit | Alexander E. Andreev, Egor A. Andreev | 2003-09-02 |
| 6557144 | Netlist resynthesis program based on physical delay calculation | Aiguo Lu, Pedja Raspopovic | 2003-04-29 |
| 6553551 | Timing recomputation | Andrej A. Zolotykh, Elyar E. Gasanov, Aiguo Lu | 2003-04-22 |
| 6550045 | Changing clock delays in an integrated circuit for skew optimization | Aiguo Lu, Andrej A. Zolotykj, Elyar E. Gasanov | 2003-04-15 |
| 6550044 | Method in integrating clock tree synthesis and timing optimization for an integrated circuit design | Aiguo Lu, Andrej A. Zolotykh, Elyar E. Gasanov | 2003-04-15 |
| 6546541 | Placement-based integrated circuit re-synthesis tool using estimated maximum interconnect capacitances | Dusan Petranovic, Aiguo Lu | 2003-04-08 |
| 6546539 | Netlist resynthesis program using structure co-factoring | Aiquo Lu, Pedja Raspopovic | 2003-04-08 |
| 6526553 | Chip core size estimation | Alexander E. Andreev, Ranko Scepanovic | 2003-02-25 |