Issued Patents 2003
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6651239 | Direct transformation of engineering change orders to synthesized IC chip designs | Andrey Nikitin, Nikola Radovanovic | 2003-11-18 |
| 6637016 | Assignment of cell coordinates | Elyar E. Gasanov, Ivan Pavisic, Aiguo Lu | 2003-10-21 |
| 6637011 | Method and apparatus for quick search for identities applicable to specified formula | Elyar E. Gasanov, Alexander S. Podkolzin, Valery B. Kudryavtsev | 2003-10-21 |
| 6629304 | Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cells | Elyar E. Gasanov, Aiguo Lu, Ivan Pavisic | 2003-09-30 |
| 6564361 | Method and apparatus for timing driven resynthesis | Elyar E. Gasanov, Alexander S. Podkolzin, Valery B. Kudryavtsev | 2003-05-13 |
| 6553551 | Timing recomputation | Elyar E. Gasanov, Ivan Pavisic, Aiguo Lu | 2003-04-22 |
| 6550044 | Method in integrating clock tree synthesis and timing optimization for an integrated circuit design | Ivan Pavisic, Aiguo Lu, Elyar E. Gasanov | 2003-04-15 |
| 6543032 | Method and apparatus for local resynthesis of logic trees with multiple cost functions | Elyar E. Gasanov, Alexander S. Podkolzin, Valery B. Kudryavtsev | 2003-04-01 |
| 6532582 | Method and apparatus for optimal critical netlist area selection | Elyar E. Gasanov, Alexander S. Podkolzin, Valery B. Kudryavtsev | 2003-03-11 |