RN

Ronald J. Nagahara

Lsi Logic: 3 patents #31 of 388Top 8%
📍 San Jose, CA: #225 of 2,494 inventorsTop 10%
🗺 California: #2,144 of 26,763 inventorsTop 9%
Overall (2002): #21,873 of 266,432Top 9%
3
Patents 2002

Issued Patents 2002

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
6489242 Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures Jayanthi Pallinti, Dawn M. Lee 2002-12-03
6417093 Process for planarization of metal-filled trenches of integrated circuit structures by forming a layer of planarizable material over the metal layer prior to planarizing James J. Xie, Jayanthi Pallinti, Akihisa Ueno 2002-07-09
6372524 Method for CMP endpoint detection James J. Xie, Jayanthi Pallinti 2002-04-16