JX

James J. Xie

Lsi Logic: 2 patents #56 of 388Top 15%
📍 San Jose, CA: #402 of 2,494 inventorsTop 20%
🗺 California: #3,859 of 26,763 inventorsTop 15%
Overall (2002): #59,963 of 266,432Top 25%
2
Patents 2002

Issued Patents 2002

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
6417093 Process for planarization of metal-filled trenches of integrated circuit structures by forming a layer of planarizable material over the metal layer prior to planarizing Ronald J. Nagahara, Jayanthi Pallinti, Akihisa Ueno 2002-07-09
6372524 Method for CMP endpoint detection Jayanthi Pallinti, Ronald J. Nagahara 2002-04-16