DL

Dawn M. Lee

Lsi Logic: 2 patents #56 of 388Top 15%
📍 San Jose, CA: #402 of 2,494 inventorsTop 20%
🗺 California: #3,859 of 26,763 inventorsTop 15%
Overall (2002): #68,979 of 266,432Top 30%
2
Patents 2002

Issued Patents 2002

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
6489242 Process for planarization of integrated circuit structure which inhibits cracking of low dielectric constant dielectric material adjacent underlying raised structures Ronald J. Nagahara, Jayanthi Pallinti 2002-12-03
6391768 Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure Jayanthi Pallinti, Weidan Li, Ming-Yi Lee 2002-05-21