Issued Patents 2002
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6492684 | Silicon-on-insulator chip having an isolation barrier for reliability | Ronald J. Bolam, Subhash B. Kulkarni | 2002-12-10 |
| 6451634 | Method of fabricating a multistack 3-dimensional high density semiconductor device | William H. Ma | 2002-09-17 |
| 6440807 | Surface engineering to prevent EPI growth on gate poly during selective EPI processing | Atul Ajmera, Michael D. Steigerwalt | 2002-08-27 |
| 6437377 | Low dielectric constant sidewall spacer using notch gate process | Atul Ajmera, Ka-Hing Fung, Victor Ku | 2002-08-20 |
| 6429084 | MOS transistors with raised sources and drains | Heemyong Park, Fariborz Assaderaghi | 2002-08-06 |
| 6429488 | Densely patterned silicon-on-insulator (SOI) region on a wafer | Effendi Leobandung, Devendra K. Sadana, Ghavam G. Shahidi | 2002-08-06 |
| 6404014 | Planar and densely patterned silicon-on-insulator structure | Effendi Leobandung, Devendra K. Sadana, Ghavam G. Shahidi | 2002-06-11 |
| 6395587 | Fully amorphized source/drain for leaky junctions | Scott W. Crowder, Melanie J. Sherony | 2002-05-28 |
| 6387742 | Thermal conductivity enhanced semiconductor structures and fabrication processes | Robert J. Gauthier, Jr., William R. Tonti, Steven H. Voldman | 2002-05-14 |
| 6352905 | Method and structure of high and low K buried oxide for SOI technology | Robert J. Gauthier, Jr., Steven H. Voldman | 2002-03-05 |
| 6339005 | Disposable spacer for symmetric and asymmetric Schottky contact to SOI MOSFET | Andres Bryant, Jerome B. Lasky, Effendi Leobandung | 2002-01-15 |