Issued Patents 1997
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5702989 | Method for fabricating a tub structured stacked capacitor for a DRAM cell having a central column | Chen-Jong Wang | 1997-12-30 |
| 5702988 | Blending integrated circuit technology | — | 1997-12-30 |
| 5693974 | Elevated source/drain with solid phase diffused source/drain extension for deep sub-micron MOSFETS | Ching-Hsiang Hsu | 1997-12-02 |
| 5686335 | Method of making high-performance and reliable thin film transistor (TFT) using plasma hydrogenation with a metal shield on the TFT channel | Shou-Gwo Wuu, Kan-Yuan Lee | 1997-11-11 |
| 5679591 | Method of making raised-bitline contactless trenched flash memory cell | Ruei-Ling Lin, Ching-Hsiang Hsu | 1997-10-21 |
| 5677557 | Method for forming buried plug contacts on semiconductor integrated circuits | Shou-Gwo Wuu, Chen-Jong Wang, Chung-Hui Su | 1997-10-14 |
| 5672896 | Three stage ESD protection device | Jin-Yuan Lee | 1997-09-30 |
| 5670431 | Method of forming an ultra thin dielectric film for a capacitor | Julie Huanga | 1997-09-23 |
| 5668038 | One step smooth cylinder surface formation process in stacked cylindrical DRAM products | Yuan-Chang Huang, Chen-Jong Wang | 1997-09-16 |
| 5668380 | Reduced area metal contact to a thin polysilicon layer contact structure having low ohmic resistance | Shou-Gwo Wuu, Chung-Hui Su, Chen-Jong Wang | 1997-09-16 |
| 5668035 | Method for fabricating a dual-gate dielectric module for memory with embedded logic technology | Chung Hsin Fang, Julie Huang, Chen-Jong Wang | 1997-09-16 |
| 5656546 | Self-aligned tin formation by N.sub.2.sup.+ implantation during two-step annealing Ti-salicidation | Chii-Wen Chen | 1997-08-12 |
| 5654231 | Method of eliminating buried contact trench in SRAM technology | Jin-Yuan Lee, Chun-Yi Shih | 1997-08-05 |
| 5652174 | Unified stacked contact process for static random access memory (SRAM) having polysilicon load resistors | Shou-Gwo Wuu, Chung-Hui Su, Chen-Jong Wang | 1997-07-29 |
| 5646435 | Method for fabricating CMOS field effect transistors having sub-quarter micrometer channel lengths with improved short channel effect characteristics | Charles C. Hsu | 1997-07-08 |
| 5646061 | Two-layer polysilicon process for forming a stacked DRAM capacitor with improved doping uniformity and a controllable shallow junction contact | Chen-Jong Wang | 1997-07-08 |
| 5644269 | Cascode MOS current mirror with lateral bipolar junction transistor to enhance ouput signal swing | Shyh-Chyi Wong | 1997-07-01 |
| 5623153 | Sub-quarter micrometer channel field effect transistor having elevated source/drain areas and lightly doped drains | Charles C. Hsu | 1997-04-22 |
| 5616951 | Dielectric as load resistor in 4T SRAM | — | 1997-04-01 |
| 5614424 | Method for fabricating an accumulated-base bipolar junction transistor | Shyh-Chyi Wong | 1997-03-25 |
| 5614430 | Anti-punchthrough ion implantation for sub-half micron channel length MOSFET devices | Jin-Yuan Lee | 1997-03-25 |
| 5610087 | Method for fabricating narrow base width lateral bipolar junction transistor, on SOI layer | Ching-Hsiang Hsu, Shyh-Chyi Wong, Steve S. Chung | 1997-03-11 |
| 5607874 | Method for fabricating a DRAM cell with a T shaped storage capacitor | Chen-Jong Wang | 1997-03-04 |
| 5607879 | Method for forming buried plug contacts on semiconductor integrated circuits | Shou-Gwo Wuu, Chen-Jong Wang, Chung-Hui Su | 1997-03-04 |
| 5605853 | Method of making a semiconductor device having 4 transistor SRAM and floating gate memory cells | Chue-San Yoo, Jin-Yuan Lee | 1997-02-25 |