Issued Patents 1997
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5702980 | Method for forming intermetal dielectric with SOG etchback and CMP | Sylin-Ming Jang | 1997-12-30 |
| 5702977 | Shallow trench isolation method employing self-aligned and planarized trench fill dielectric layer | Syun-Ming Jang, Ying-Ho Chen | 1997-12-30 |
| 5700737 | PECVD silicon nitride for etch stop mask and ozone TEOS pattern sensitivity elimination | Syun-Ming Jang | 1997-12-23 |
| 5679606 | method of forming inter-metal-dielectric structure | Chin-Kun Wang, Lu-Min Lin | 1997-10-21 |
| 5674783 | Method for improving the chemical-mechanical polish (CMP) uniformity of insulator layers | Syun-Ming Jang | 1997-10-07 |
| 5674784 | Method for forming polish stop layer for CMP process | Syun-Ming Jang | 1997-10-07 |
| 5656545 | Elimination of tungsten dimple for stacked contact or via application | — | 1997-08-12 |
| 5654233 | Step coverage enhancement process for sub half micron contact/via | — | 1997-08-05 |
| 5654240 | Integrated circuit fabrication having contact opening | Kuo-Hua Lee | 1997-08-05 |
| 5654234 | Method for forming a void-free tungsten-plug contact in the presence of a contact opening overhang | Tsu Shih | 1997-08-05 |
| 5631197 | Sacrificial etchback layer for improved spin-on-glass planarization | Syun-Ming Jang, Lung Chen, Yuan-Chang Huang | 1997-05-20 |
| 5599740 | Deposit-etch-deposit ozone/teos insulator layer method | Syun-Ming Jang | 1997-02-04 |
| 5599730 | Poly-buffered LOCOS | Kuo-Hua Lee | 1997-02-04 |
| 5591674 | Integrated circuit with silicon contact to silicide | Kuo-Hua Lee | 1997-01-07 |