Issued Patents 1997
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5651124 | Processor structure and method for aggressively scheduling long latency instructions including load/store instructions while maintaining precise state | Gene W. Shen, John Szeto, Niteen A. Patkar, Michael C. Shebanow | 1997-07-22 |
| 5638312 | Method and apparatus for generating a zero bit status flag in a microprocessor | — | 1997-06-10 |