Issued Patents 1997
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5675759 | Method and apparatus for register management using issue sequence prior physical register and register association validity information | Michael C. Shebanow, Gene W. Shen, Ravi Swami | 1997-10-07 |
| 5659721 | Processor structure and method for checkpointing instructions to maintain precise state | Gene W. Shen, John Szeto, Michael C. Shebanow | 1997-08-19 |
| 5651124 | Processor structure and method for aggressively scheduling long latency instructions including load/store instructions while maintaining precise state | Gene W. Shen, John Szeto, Michael C. Shebanow, Michael A. Simone | 1997-07-22 |
| 5649136 | Processor structure and method for maintaining and restoring precise state at any instruction boundary | Gene W. Shen, John Szeto, Michael C. Shebanow | 1997-07-15 |
| 5644742 | Processor structure and method for a time-out checkpoint | Gene W. Shen, John Szeto, Michael C. Shebanow | 1997-07-01 |
| 5632028 | Hardware support for fast software emulation of unimplemented instructions | Shalesh Thusoo, Farnad Sajjadian, Jaspal Kohli | 1997-05-20 |