Issued Patents All Time
Showing 76–100 of 106 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6316352 | Method of fabricating a bottom electrode | King-Lung Wu | 2001-11-13 |
| 6312985 | Method of fabricating a bottom electrode | King-Lung Wu | 2001-11-06 |
| 6291281 | Method of fabricating protection structure | Mu-Chun Wang | 2001-09-18 |
| 6287751 | Method of fabricating contact window | Li-Chieh Chao, Chun-Te Chen | 2001-09-11 |
| 6287923 | Method of forming a MOS transistor | — | 2001-09-11 |
| 6284647 | Method to improve the uniformity of chemical mechanical polishing | Sun-Chieh Chien, Chien-Li Kuo, Wei-Wu Liao | 2001-09-04 |
| 6281081 | Method of preventing current leakage around a shallow trench isolation structure | Sun-Chieh Chien, Chien-Li Kuo, Wei-Wu Liao | 2001-08-28 |
| 6261968 | Method of forming a self-aligned contact hole on a semiconductor wafer | — | 2001-07-17 |
| 6245610 | Method of protecting a well at a floating stage | Mu-Chun Wang, Shiang Huang-Lu | 2001-06-12 |
| 6235642 | Method for reducing plasma charging damages | Mu-Chun Wang | 2001-05-22 |
| 6218271 | Method of forming a landing pad on the drain and source of a MOS transistor | Kun-Chi Lin | 2001-04-17 |
| 6211086 | Method of avoiding CMP caused residue on wafer edge uncompleted field | Horng-Nan Chern | 2001-04-03 |
| 6200880 | Method for forming shallow trench isolation | Sun-Chieh Chien, Chien-Li Kuo, Wei-Wu Liao | 2001-03-13 |
| 6184126 | Fabricating method of dual damascene | Li-Chieh Chao | 2001-02-06 |
| 6177342 | Method of forming dual damascene interconnects using glue material as plug material | Li-Chieh Chao | 2001-01-23 |
| 6171951 | Dual damascene method comprising ion implanting to densify dielectric layer and forming a hard mask layer with a tapered opening | Tse-Yi Lu | 2001-01-09 |
| 6165879 | Method for improving manufacturing process of self-aligned contact | Hsi-Chien Lin | 2000-12-26 |
| 6160314 | Polishing stop structure | Li-Chieh Chao | 2000-12-12 |
| 6159797 | Method of fabricating a flash memory with a planarized topography | — | 2000-12-12 |
| 6159850 | Method for reducing resistance of contact window | Chien-Li Kuo | 2000-12-12 |
| 6146971 | Process for forming a shallow trench isolation structure | Chun-Lung Chen, Hsi-Mao Hsiao, Hung-Chen Yu | 2000-11-14 |
| 6121125 | Method of forming polycide gate | — | 2000-09-19 |
| 6100158 | Method of manufacturing an alignment mark with an etched back dielectric layer and a transparent dielectric layer and a device region on a higher plane with a wiring layer and an isolation region | Kun-Chi Lin, Horng-Nan Chern, Alex Hou | 2000-08-08 |
| 6074923 | Method of fabricating metal-oxide-semiconductor transistor | — | 2000-06-13 |
| 6071769 | Method for forming a resistor load of a static random access memory | Han-Chung Lin | 2000-06-06 |