Issued Patents All Time
Showing 51–75 of 100 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5661047 | Method for forming bipolar ROM device | Chen-Chiu Hsue | 1997-08-26 |
| 5656840 | Single bit erase flash EEPROM | — | 1997-08-12 |
| 5650346 | Method of forming MOSFET devices with buried bitline capacitors | Hong-Tsz Pan, Chung-Cheng Wu | 1997-07-22 |
| 5650657 | Protection from short circuits between P and N wells | — | 1997-07-22 |
| 5633520 | Neuron MOSFET with different interpolysilicon oxide | Chung-Cheng Wu | 1997-05-27 |
| 5629220 | Method of manufacture of pull down transistor with drain off-set for low leakage SRAM's | — | 1997-05-13 |
| 5604367 | Compact EEPROM memory cell having a floating gate transistor with a multilayer gate electrode | — | 1997-02-18 |
| 5592011 | Single layer thin film transistor static random access memory cell | — | 1997-01-07 |
| 5591549 | Self aligning fabrication method for sub-resolution phase shift mask | — | 1997-01-07 |
| 5587600 | Series MOS ROM with tapered oxide side walls | — | 1996-12-24 |
| 5578857 | Double poly high density buried bit line mask ROM | Gary Hong, Chen-Chiu Hsue | 1996-11-26 |
| 5572056 | High density ROM | Chen-Chiu Hsue, Te-Sun Wu | 1996-11-05 |
| 5569962 | Split polysilicon SRAM cell | — | 1996-10-29 |
| 5554545 | Method of forming neuron mosfet with different interpolysilicon oxide thickness | Chung-Cheng Wu | 1996-09-10 |
| 5541876 | Memory cell fabricated by floating gate structure | Chen-Chin Hsue, Chung-Cheng Wu | 1996-07-30 |
| 5533634 | Quantum chromeless lithography | Hong-Tsz Pan, Shyi-Long Shy | 1996-07-09 |
| 5516713 | Method of making high coupling ratio NAND type flash memory | Chen-Chiu Hsue | 1996-05-14 |
| 5510214 | Double destruction phase shift mask | Hong-Tsz Pan | 1996-04-23 |
| 5496200 | Sealed vacuum electronic devices | Hong-Tsz Pan | 1996-03-05 |
| 5488004 | SOI by large angle oxygen implant | — | 1996-01-30 |
| 5482900 | Method for forming a metallurgy system having a dielectric layer that is planar and void free | — | 1996-01-09 |
| 5480822 | Method of manufacture of semiconductor memory device with multiple, orthogonally disposed conductors | Chen-Chiu Hsue | 1996-01-02 |
| 5478679 | Half-tone self-aligning phase shifting mask | Wen-An Loong, Shyi-Long Shy, Hong-Tsz Pan, Guey-Chi Guo, Yueh-Lin Chou | 1995-12-26 |
| 5478678 | Double rim phase shifter mask | Hong-Tsz Pan | 1995-12-26 |
| 5468980 | Buried bit line DRAM cell | Chen-Chiu Hsue, Gary Hong | 1995-11-21 |