Issued Patents All Time
Showing 76–100 of 100 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5461251 | Symmetric SRAM cell with buried N+ local interconnection line | Chen-Chiu Hsue | 1995-10-24 |
| 5459086 | Metal via sidewall tilt angle implant for SOG | — | 1995-10-17 |
| 5451534 | Method of making single layer thin film transistor static random access memory cell | — | 1995-09-19 |
| 5449644 | Process for contact hole formation using a sacrificial SOG layer | Gary Hong, Cheng-Han Huang, Hong-Tsz Pan | 1995-09-12 |
| 5444411 | Functional MOS transistor with gate-level weighted sum and threshold operations | Chung-Cheng Wu | 1995-08-22 |
| 5439838 | Method of thinning for EEPROM tunneling oxide device | — | 1995-08-08 |
| 5438009 | Method of fabrication of MOSFET device with buried bit line | Gary Hong | 1995-08-01 |
| 5436186 | Process for fabricating a stacked capacitor | Chen-Chiu Hsue, Gary Hong | 1995-07-25 |
| 5436190 | Method for fabricating semiconductor device isolation using double oxide spacers | Chung-Cheng Wu | 1995-07-25 |
| 5429980 | Method of forming a stacked capacitor using sidewall spacers and local oxidation | Anchor Chen, Chen-Chiu Hsue | 1995-07-04 |
| 5429971 | Method of making single bit erase flash EEPROM | — | 1995-07-04 |
| 5418176 | Process for producing memory devices having narrow buried N+ lines | Cheng-Han Huang, Chen-Chiu Hsue | 1995-05-23 |
| 5394356 | Process for forming an FET read only memory device | — | 1995-02-28 |
| 5393233 | Process for fabricating double poly high density buried bit line mask ROM | Gary Hong, Chen-Chiu Hsue | 1995-02-28 |
| 5380673 | Dram capacitor structure | Chen-Chiu Hsue, Anchor Chen | 1995-01-10 |
| 5380676 | Method of manufacturing a high density ROM | Chen-Chiu Hsue, Te-Sun Wu | 1995-01-10 |
| 5372955 | Method of making a device with protection from short circuits between P and N wells | — | 1994-12-13 |
| 5366918 | Method for fabricating a split polysilicon SRAM cell | — | 1994-11-22 |
| 5364808 | Method of making a buried bit line DRAM cell | Chen-Chiu Hsue, Gary Hong | 1994-11-15 |
| 5354704 | Symmetric SRAM cell with buried N+ local interconnection line | Chen-Chin Hsue | 1994-10-11 |
| 5350700 | Method of fabricating bipolar transistors with buried collector region | Chung-Cheng Wu | 1994-09-27 |
| 5318921 | Method for making a high density ROM or EPROM integrated circuit | Chen-Chiu Hsue | 1994-06-07 |
| 5306657 | Process for forming an FET read only memory device | — | 1994-04-26 |
| 5258634 | Electrically erasable read only memory cell array having elongated control gate in a trench | — | 1993-11-02 |
| 5180680 | Method of fabricating electrically erasable read only memory cell | — | 1993-01-19 |