Issued Patents All Time
Showing 26–50 of 148 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6219688 | Method, apparatus and system for sum of plural absolute differences | Christopher Jensen Read | 2001-04-17 |
| 6219695 | Circuits, systems, and methods for communicating computer video output to a remote location | Susan Kay Duyka Harrison, Kenneth W. Schachter | 2001-04-17 |
| 6219627 | Architecture of a chip having multiple processors and multiple memories | Walt C. Bonneau, Jr., Robert J. Gove | 2001-04-17 |
| 6173394 | Instruction having bit field designating status bits protected from modification corresponding to arithmetic logic unit result | Sydney W. Poland, Keith Balmer | 2001-01-09 |
| 6116768 | Three input arithmetic logic unit with barrel rotator | Keith Balmer, Robert J. Gove, Christopher Jensen Read, Jeremiah E. Golston, Sydney W. Poland +2 more | 2000-09-12 |
| 6098163 | Three input arithmetic logic unit with shifter | Keith Balmer, Robert J. Gove, Christopher Jensen Read, Jeremiah E. Golston, Sydney W. Poland +2 more | 2000-08-01 |
| 6088280 | High-speed memory arranged for operating synchronously with a microprocessor | Wilbur C. Vogley, Anthony M. Balistreri, Steven D. Krueger, Duy-Loan T. Le, Joseph H. Neal +3 more | 2000-07-11 |
| 6070003 | System and method of memory access in apparatus having plural processors and plural memories | Robert J. Gove, Keith Balmer, Nicholas Ing-Simmons | 2000-05-30 |
| 6058473 | Memory store from a register pair conditional upon a selected status bit | Sydney W. Poland, Keith Balmer | 2000-05-02 |
| 6032170 | Long instruction word controlling plural independent processor operations | Christopher Jensen Read, Keith Balmer | 2000-02-29 |
| 6016538 | Method, apparatus and system forming the sum of data in plural equal sections of a single data word | Christopher Jensen Read | 2000-01-18 |
| 5995747 | Three input arithmetic logic unit capable of performing all possible three operand boolean operations with shifter and/or mask generator | Keith Balmer, Robert J. Gove, Christopher Jensen Read, Jeremiah E. Golston, Sydney W. Poland +2 more | 1999-11-30 |
| 5995748 | Three input arithmetic logic unit with shifter and/or mask generator | Keith Balmer, Robert J. Gove, Christopher Jensen Read, Jeremiah E. Golston, Sydney W. Poland +2 more | 1999-11-30 |
| 5982694 | High speed memory arranged for operating synchronously with a microprocessor | Wilbur C. Vogley, Anthony M. Balistreri, Steven D. Krueger, Duy-Loan T. Le, Joseph H. Neal +3 more | 1999-11-09 |
| 5974539 | Three input arithmetic logic unit with shifter and mask generator | Keith Balmer, Robert J. Gove, Christopher Jensen Read, Jeremiah E. Golston, Sydney W. Poland +2 more | 1999-10-26 |
| 5961635 | Three input arithmetic logic unit with barrel rotator and mask generator | Keith Balmer, Robert J. Gove, Christopher Jensen Read, Jeremiah E. Golston, Sydney W. Poland +2 more | 1999-10-05 |
| 5960193 | Apparatus and system for sum of plural absolute differences | Christopher Jensen Read | 1999-09-28 |
| 5956744 | Memory configuration cache with multilevel hierarchy least recently used cache entry replacement | Iain Robertson, Eric R. Hansen | 1999-09-21 |
| 5923340 | Process of processing graphics data | Michael D. Asal, Jerry R. Van Aken, Neil Tebbutt, Mark F. Novak | 1999-07-13 |
| 5912854 | Data processing system arranged for operating synchronously with a high speed memory | Wilbur C. Vogley, Anthony M. Balistreri, Steven D. Krueger, Duy-Loan T. Le, Joseph H. Neal +3 more | 1999-06-15 |
| 5808958 | Random access memory with latency arranged for operating synchronously with a micro processor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock | Wilbur C. Vogley, Anthony M. Balistreri, Steven D. Krueger, Duy-Loan T. Le, Joseph H. Neal +3 more | 1998-09-15 |
| 5805913 | Arithmetic logic unit with conditional register source selection | Keith Balmer | 1998-09-08 |
| 5768609 | Reduced area of crossbar and method of operation | Robert J. Gove, Keith Balmer, Nicholas Ing-Simmons | 1998-06-16 |
| 5761726 | Base address generation in a multi-processing system having plural memories with a unified address space corresponding to each processor | Keith Balmer, Robert J. Gove, Christopher Jensen Read, Jeremiah E. Golston, Sydney W. Poland +2 more | 1998-06-02 |
| 5742538 | Long instruction word controlling plural independent processor operations | Christopher Jensen Read, Keith Balmer | 1998-04-21 |