Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6038645 | Microprocessor circuits, systems, and methods using a combined writeback queue and victim cache | Ashwini Nanda | 2000-03-14 |
| 6032225 | Microprocessor system with burstable, non-cacheable memory access support | Ashwini Nanda, Ian Chen, Steven D. Krueger | 2000-02-29 |
| 6029228 | Data prefetching of a load target buffer for post-branch instructions based on past prediction accuracy's of branch predictions | George Cai | 2000-02-22 |
| 5974440 | Microprocessor with circuits, systems, and methods for interrupt handling during virtual task operation | James E. Brooks, Robert R. Collins | 1999-10-26 |
| 5963721 | Microprocessor system with capability for asynchronous bus transactions | Ian Chen, Robert W. Milhaupt | 1999-10-05 |
| 5961632 | Microprocessor with circuits, systems, and methods for selecting alternative pipeline instruction paths based on instruction leading codes | Donald E. Steiss | 1999-10-05 |
| 5958046 | Microprocessor with reduced microcode space requirements due to improved branch target microaddress circuits, systems, and methods | James O. Bondi | 1999-09-28 |
| 5954812 | Apparatus for caching system management memory in a computer having a system management mode employing address translation | Patrick W. Bosshart | 1999-09-21 |
| 5951679 | Microprocessor circuits, systems, and methods for issuing successive iterations of a short backward branch loop in a single cycle | Timothy David Anderson | 1999-09-14 |
| 5951677 | Efficient hardware implementation of euclidean array processing in reed-solomon decoding | Tod D. Wolf | 1999-09-14 |
| 5953512 | Microprocessor circuits, systems, and methods implementing a loop and/or stride predicting load target buffer | George Cai | 1999-09-14 |
| 5950012 | Single chip microprocessor circuits, systems, and methods for self-loading patch micro-operation codes and patch microinstruction codes | Ian Chen | 1999-09-07 |
| 5935241 | Multiple global pattern history tables for branch prediction in a microprocessor | George Cai | 1999-08-10 |
| 5913049 | Multi-stream complex instruction set microprocessor | Donald E. Steiss | 1999-06-15 |
| 5911057 | Superscalar microprocessor having combined register and memory renaming circuits, systems, and methods | — | 1999-06-08 |
| 5909566 | Microprocessor circuits, systems, and methods for speculatively executing an instruction using its most recently used data while concurrently prefetching data for the instruction | George Cai | 1999-06-01 |
| 5903742 | Method and circuit for redefining bits in a control register | Donald E. Steiss | 1999-05-11 |
| 5864697 | Microprocessor using combined actual and speculative branch history prediction | — | 1999-01-26 |
| 5850543 | Microprocessor with speculative instruction pipelining storing a speculative register value within branch target buffer for use in speculatively executing instructions after a return | Donald E. Steiss | 1998-12-15 |
| 5826084 | Microprocessor with circuits, systems, and methods for selectively bypassing external interrupts past the monitor program during virtual program operation | James E. Brooks, Robert R. Collins | 1998-10-20 |
| 5815697 | Circuits, systems, and methods for reducing microprogram memory power for multiway branching | Patrick W. Bosshart | 1998-09-29 |
| 5799180 | Microprocessor circuits, systems, and methods passing intermediate instructions between a short forward conditional branch instruction and target instruction through pipeline, then suppressing results if branch taken | James O. Bondi | 1998-08-25 |