Issued Patents All Time
Showing 51–75 of 86 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5859807 | Semiconductor integrated circuit device having a controlled overdriving circuit | Hiroshi Otori, Takesada Akiba, Goro Kitsukawa | 1999-01-12 |
| 5841688 | Matched delay word line strap | Shunichi Sukegawa, Tadashi Tachibana, Katsuo Komatsuzaki, Takeshi Sakai | 1998-11-24 |
| 5831919 | Apparatus and method for a direct-sense sense-amplifier with decoded read and write Y-select | Brent Haukness | 1998-11-03 |
| 5802005 | Four bit pre-fetch sDRAM column select architecture | Masayuki Nakamura, Jeffrey E. Koelling, Paulette Thurston | 1998-09-01 |
| 5792682 | Method for reducing charge loss | Jeffrey E. Koelling | 1998-08-11 |
| 5790467 | Apparatus and method for a direct-sense sense amplifier with a single read/write control line | Brent Haukness | 1998-08-04 |
| 5696721 | Dynamic random access memory having row decoder with level translator for driving a word line voltage above and below an operating supply voltage range | Jeffrey E. Koelling | 1997-12-09 |
| 5642321 | Voltage level detection circuit | — | 1997-06-24 |
| 5553033 | Apparatus and method for an address transition detector summing circuit | — | 1996-09-03 |
| 5519666 | Apparatus and method for an address transition detector | — | 1996-05-21 |
| 5502671 | Apparatus and method for a semiconductor memory configuration-dependent output buffer supply circuit | Jeffrey E. Koelling | 1996-03-26 |
| 5353250 | Pin programmable dram that provides customer option programmability | — | 1994-10-04 |
| 5347173 | Dynamic memory, a power up detection circuit, and a level detection circuit | — | 1994-09-13 |
| 5309446 | Test validation method for a semiconductor memory device | Danny R. Cline, Wah Kit Loh, Adin E. Hyslop, Chok Y. Hung | 1994-05-03 |
| 5303180 | Pin programmable dram that allows customer to program option desired | — | 1994-04-12 |
| 5301160 | Computer including an integrated circuit having a low power selection control arrangement | — | 1994-04-05 |
| 5297086 | Method for initializing redundant circuitry | Takumi Nasu | 1994-03-22 |
| 5274828 | Computer including an integrated circuit having an on-chip high voltage source | — | 1993-12-28 |
| 5270975 | Memory device having a non-uniform redundancy decoder arrangement | — | 1993-12-14 |
| 5220534 | Substrate bias generator system | Wah Kit Loh, Narasimhan Iyengar, Danny R. Cline | 1993-06-15 |
| 5208776 | Pulse generation circuit | Takumi Nasu | 1993-05-04 |
| 5191555 | CMOS single input buffer for multiplexed inputs | Paolo Tabacco, Carol A. Price | 1993-03-02 |
| 5131018 | Counter circuit with two tri-state latches | Paolo Tabacco | 1992-07-14 |
| 5117426 | Circuit, device, and method to detect voltage leakage | — | 1992-05-26 |
| 5034623 | Low power, TTL level CMOS input buffer with hysteresis | — | 1991-07-23 |