Issued Patents All Time
Showing 1–25 of 34 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12411694 | Processor having adaptive pipeline with latency reduction logic that selectively executes instructions to reduce latency | Shrey Bhatia, Jeroen Vliegen | 2025-09-09 |
| 12353308 | Processor with debug pipeline | Shrey Bhatia, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch | 2025-07-08 |
| 11934245 | Microcontroller energy profiler | Hans Van Antwerpen, Stephan Rosner, Roland Richter, Jean-Paul Vanitegem, Jan-Willem van de Waerdt | 2024-03-19 |
| 11868780 | Central processor-coprocessor synchronization | Armin Stingl, Jeroen Vliegen | 2024-01-09 |
| 11861367 | Processor with variable pre-fetch threshold | Johann Zipperer | 2024-01-02 |
| 11803455 | Processor with debug pipeline | Shrey Bhatia, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch | 2023-10-31 |
| 11645083 | Processor having adaptive pipeline with latency reduction logic that selectively executes instructions to reduce latency | Shrey Bhatia, Jeroen Vilegen | 2023-05-09 |
| 11593241 | Processor with debug pipeline | Shrey Bhatia, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch | 2023-02-28 |
| 11513804 | Pipeline flattener with conditional triggers | Markus Koesler, Johann Zipperer, Wolfgang Lutsch | 2022-11-29 |
| 11308008 | Systems and methods for handling DPI messages outgoing from an emulator system | Mitchell G. Poplack, Bhoumik Shah, Ping-Sheng Tseng | 2022-04-19 |
| 11231933 | Processor with variable pre-fetch threshold | Johann Zipperer | 2022-01-25 |
| 11150906 | Processor with a full instruction set decoder and a partial instruction set decoder | Shrey Bhatia | 2021-10-19 |
| 11132203 | System and method for synchronizing instruction execution between a central processor and a coprocessor | Armin Stingl, Jeroen Vliegen | 2021-09-28 |
| 11023025 | Microcontroller energy profiler | Hans Van Antwerpen, Stephan Rosner, Roland Richter, Jean-Paul Vanitegem, Jan-Willem van de Waerdt | 2021-06-01 |
| 10929101 | Processor with efficient arithmetic units | Armin Stingl | 2021-02-23 |
| 10891207 | Processor with debug pipeline | Shrey Bhatia, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch | 2021-01-12 |
| 10795685 | Operating a pipeline flattener in order to track instructions for complex | Markus Koesler, Johann Zipperer, Wolfgang Lutsch | 2020-10-06 |
| 10740105 | Processor subroutine cache | — | 2020-08-11 |
| 10628163 | Processor with variable pre-fetch threshold | Johann Zipperer | 2020-04-21 |
| 10437596 | Processor with a full instruction set decoder and a partial instruction set decoder | Shrey Bhatia | 2019-10-08 |
| 10255078 | Operating a pipeline flattener in order to track instructions for complex breakpoints | Markus Koesler, Johann Zipperer, Wolfgang Lutsch | 2019-04-09 |
| 10049025 | Processor with debug pipeline | Shrey Bhatia, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch | 2018-08-14 |
| 10042605 | Processor with efficient arithmetic units | Armin Stingl | 2018-08-07 |
| 9645825 | Instruction cache with access locking | Max Gröning, Norbert Reichel | 2017-05-09 |
| 9507600 | Processor loop buffer | Ralph Ledwa, Norbert Reichel | 2016-11-29 |