| 12411694 |
Processor having adaptive pipeline with latency reduction logic that selectively executes instructions to reduce latency |
Christian Wiencke, Jeroen Vliegen |
2025-09-09 |
| 12353308 |
Processor with debug pipeline |
Christian Wiencke, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch |
2025-07-08 |
| 11803455 |
Processor with debug pipeline |
Christian Wiencke, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch |
2023-10-31 |
| 11645083 |
Processor having adaptive pipeline with latency reduction logic that selectively executes instructions to reduce latency |
Christian Wiencke, Jeroen Vilegen |
2023-05-09 |
| 11593241 |
Processor with debug pipeline |
Christian Wiencke, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch |
2023-02-28 |
| 11150906 |
Processor with a full instruction set decoder and a partial instruction set decoder |
Christian Wiencke |
2021-10-19 |
| 10891207 |
Processor with debug pipeline |
Christian Wiencke, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch |
2021-01-12 |
| 10437596 |
Processor with a full instruction set decoder and a partial instruction set decoder |
Christian Wiencke |
2019-10-08 |
| 10049025 |
Processor with debug pipeline |
Christian Wiencke, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch |
2018-08-14 |
| 9395985 |
Efficient central processing unit (CPU) return address and instruction cache |
Christian Wiencke |
2016-07-19 |
| 9384109 |
Processor with debug pipeline |
Christian Wiencke, Armin Stingl, Ralph Ledwa, Wolfgang Lutsch |
2016-07-05 |