Issued Patents All Time
Showing 26–50 of 107 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11104573 | Semiconductor arrangement with one or more semiconductor columns | Jean-Pierre Colinge, Chih-Hao Wang, Carlos H. Diaz | 2021-08-31 |
| 11038052 | Semiconductor arrangement with one or more semiconductor columns | Jean-Pierre Colinge, Kuo-Cheng Ching, Carlos H. Diaz | 2021-06-15 |
| 11011545 | Semiconductor device including standard cells | Lee-Chung Lu, Li-Chun Tien | 2021-05-18 |
| 10998340 | Semiconductor device including standard cells having different cell height | Lee-Chung Lu, Li-Chun Tien | 2021-05-04 |
| 10985159 | Method for manufacturing monolithic three-dimensional (3D) integrated circuits | Jean-Pierre Colinge, Carlos H. Diaz | 2021-04-20 |
| 10964691 | Method for manufacturing monolithic three-dimensional (3D) integrated circuits | Jean-Pierre Colinge, Carlos H. Diaz | 2021-03-30 |
| 10950540 | Enhancing integrated circuit density with active atomic reservoir | Ming-Hsien Lin | 2021-03-16 |
| 10951201 | Flip flop standard cell | Nick Samra, Stefan Rusu | 2021-03-16 |
| 10854721 | Semiconductor device with silicide | Jean-Pierre Colinge, Kuo-Cheng Ching, Carlos H. Diaz | 2020-12-01 |
| 10763198 | Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure | Carlos H. Diaz, Jean-Pierre Colinge, Yi-Hsiung Lin | 2020-09-01 |
| 10741540 | Integrated circuit layout method and device | Chien-Ying Chen, Lee-Chung Lu, Li-Chun Tien | 2020-08-11 |
| 10705766 | 3D cross-bar nonvolatile memory | Jean-Pierre Colinge, Carlos H. Diaz | 2020-07-07 |
| 10699956 | Method of manufacturing a semiconductor device and a semiconductor device | Hung-Li Chiang, Chao-Ching Cheng, Chih-Liang Chen, Tzu-Chiang Chen, Yu-Lin Yang +2 more | 2020-06-30 |
| 10686428 | Cell of transmission gate free circuit and integrated circuit layout including the same | Chi-Lin Liu, Shang-Chih Hsieh, Jerry Chang Jui Kao, Li-Chun Tien, Lee-Chung Lu | 2020-06-16 |
| 10644168 | 2-D material transistor with vertical structure | Jean-Pierre Colinge, Chung-Cheng Wu, Carlos H. Diaz, Chih-Hao Wang, Ken-Ichi Goto +3 more | 2020-05-05 |
| 10559563 | Method for manufacturing monolithic three-dimensional (3D) integrated circuits | Jean-Pierre Colinge, Carlos H. Diaz | 2020-02-11 |
| 10535655 | Integrated circuits and manufacturing methods thereof | Ali Keshavarzi, Shu-Hui Sung, Hsiang-Jen Tseng, Shyue-Shyh Lin, Lee-Chung Lu +6 more | 2020-01-14 |
| 10510744 | Vertical nanowire transistor for input/output structure | Jean-Pierre Colinge, Carlos H. Diaz | 2019-12-17 |
| 10453522 | SRAM with stacked bit cells | Carlos H. Diaz, Chih-Hao Wang, Jean-Pierre Colinge | 2019-10-22 |
| 10403550 | Method of manufacturing a semiconductor device and a semiconductor device | Hung-Li Chiang, Chao-Ching Cheng, Chih-Liang Chen, Tzu-Chiang Chen, Yu-Lin Yang +2 more | 2019-09-03 |
| 10325989 | Semiconductor device with silicide | Jean-Pierre Colinge, Kuo-Cheng Ching, Carlos H. Diaz | 2019-06-18 |
| 10312189 | Enhancing integrated circuit density with active atomic reservoir | Ming-Hsien Lin | 2019-06-04 |
| 10294101 | Semiconductor arrangement with one or more semiconductor columns | Jean-Pierre Colinge, Chih-Hao Wang, Carlos H. Diaz | 2019-05-21 |
| 10290737 | Semiconductor arrangement with one or more semiconductor columns | Jean-Pierre Colinge, Kuo-Cheng Ching, Carlos H. Diaz | 2019-05-14 |
| 10270430 | Cell of transmission gate free circuit and integrated circuit and integrated circuit layout including the same | Chi-Lin Liu, Shang-Chih Hsieh, Jerry Chang Jui Kao, Li-Chun Tien, Lee-Chung Lu | 2019-04-23 |