Issued Patents All Time
Showing 26–50 of 100 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10008501 | Sandwich EPI channel for device enhancement | Ru-Shang Hsiao, Chih-Mu Huang, Cing-Yao Chan, Chun-Ying Wang, Jen-Pan Wang | 2018-06-26 |
| 9978604 | Salicide formation using a cap layer | Mei-Hsuan Lin, Chih-Hsun Lin, Ching-Hua Chu | 2018-05-22 |
| 9893150 | Structure and method for semiconductor device | Chen-Chieh Chiang, Chih-Kang Chao, Chih-Mu Huang, Ru-Shang Hsiao | 2018-02-13 |
| 9837348 | Voids in interconnect structures and methods for forming the same | Jiun-Jie Huang | 2017-12-05 |
| 9831314 | Surface profile for semiconductor region | Chao-Hsuing Chen, Chi-Yen Lin | 2017-11-28 |
| 9818704 | Stress tuning for reducing wafer warpage | Yung-Yao Wang, Ying-Han Chiou | 2017-11-14 |
| 9735252 | V-shaped SiGe recess volume trim for improved device performance and layout dependence | Chao-Hsuing Chen, Chi-Yen Lin | 2017-08-15 |
| 9722082 | Methods and apparatus for doped SiGe source/drain stressor deposition | Chao-Hsuing Chen, Chi-Yen Lin | 2017-08-01 |
| 9634122 | Device boost by quasi-FinFET | Ru-Shang Hsiao, Chih-Mu Huang, Chia-Ming Chang | 2017-04-25 |
| 9564487 | Dual vertical channel | Ru-Shang Hsiao, Chia-Ming Chang, Huang Jiun-Jie | 2017-02-07 |
| 9543399 | Device having sloped gate profile and method of manufacture | Ru-Shang Hsiao, Chih-Mu Huang, Yao-Tsung Chen, Ming-Tsang Tsai, Kuan-Yu Chen | 2017-01-10 |
| 9484303 | Stress tuning for reducing wafer warpage | Yung-Yao Wang, Ying-Han Chiou | 2016-11-01 |
| 9466670 | Sandwich epi channel for device enhancement | Ru-Shang Hsiao, Chih-Mu Huang, Cing-Yao Chan, Chun-Ying Wang, Jen-Pan Wang | 2016-10-11 |
| 9385215 | V-shaped SiGe recess volume trim for improved device performance and layout dependence | Chao-Hsuing Chen, Chi-Yen Lin | 2016-07-05 |
| 9343318 | Salicide formation using a cap layer | Mei-Hsuan Lin, Chih-Hsun Lin, Ching-Hua Chu | 2016-05-17 |
| 9324836 | Methods and apparatus for doped SiGe source/drain stressor deposition | Chao-Hsuing Chen, Chi-Yen Lin | 2016-04-26 |
| 9318371 | Shallow trench isolation structure | Ru-Shang Hsiao, Chih-Mu Huang, Chih-Fu Chang | 2016-04-19 |
| 9310425 | Reliability assessment of capacitor device | Huang Jiun-Jie, Chi-Yen Lin, Chih-Fu Chang | 2016-04-12 |
| 9269812 | Semiconductor device having V-shaped region | Chao-Hsuing Chen, Chi-Yen Lin | 2016-02-23 |
| 9246002 | Structure and method for semiconductor device | Ru-Shang Hsiao, Chih-Mu Huang, Chih-Kang Chao, Chen-Chieh Chiang | 2016-01-26 |
| 9217917 | Three-direction alignment mark | Ru-Shang Hsiao, I-I Cheng, Jia-Ming Huang, Jen-Pan Wang, Chih-Mu Huang | 2015-12-22 |
| 9209304 | N/P MOS FinFET performance enhancement by specific orientation surface | Ru-Shang Hsiao, Hung-Pin Chen, Wei-Barn Chen, Chih-Fu Chang, Chih-Kang Chao | 2015-12-08 |
| 9209270 | MOS devices having non-uniform stressor doping | Mei-Hsuan Lin, Chih-Hsun Lin, Ching-Hua Chu | 2015-12-08 |
| 9196545 | SiGe SRAM butted contact resistance improvement | Chao-Hsuing Chen, Chi-Yen Lin | 2015-11-24 |
| 9142642 | Methods and apparatus for doped SiGe source/drain stressor deposition | Chao-Hsuing Chen, Chi-Yen Lin | 2015-09-22 |