Issued Patents All Time
Showing 26–50 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10910223 | Doping through diffusion and epitaxy profile shaping | Chih-Teng Liao, Yi-Wei Chiu, Chih Hsuan Cheng | 2021-02-02 |
| 10879109 | Method for forming semiconductor device structure | Xi-Zong Chen, Chih-Hsuan Lin, Cha-Hsin Chao, Yi-Wei Chiu | 2020-12-29 |
| 10825727 | Metal gates of transistors having reduced resistivity | Chia-Ching Tsai, Yi-Wei Chiu | 2020-11-03 |
| 10804149 | Self-aligned spacers and method forming same | Yi-Tsang Hsieh, Cha-Hsin Chao, Yi-Wei Chiu, Ying Ting Hsia | 2020-10-13 |
| 10763162 | Interconnect structure of semiconductor device | Chia-Ching Tsai, Yi-Wei Chiu | 2020-09-01 |
| 10692762 | Semiconductor device with gate stack | Hua-Li Hung, Chih-Lun Lu, Hsu-Yu Huang, Tsung Fan Yin, Ying Ting Hsia +1 more | 2020-06-23 |
| 10679896 | Contact structure for semiconductor device | Yun-Yu Hsieh, Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Ying Ting Hsia | 2020-06-09 |
| 10679891 | Methods of forming interconnect structures using a vacuum environment | Chia-Ching Tsai, Yi-Wei Chiu, Hung Jui Chang | 2020-06-09 |
| 10651079 | Semiconductor device and manufacturing method thereof | Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Ying Ting Hsia | 2020-05-12 |
| 10629480 | Method for forming semiconductor device structure | Xi-Zong Chen, Chih-Hsuan Lin, Cha-Hsin Chao, Yi-Wei Chiu | 2020-04-21 |
| 10515817 | Method for forming features of semiconductor structure having reduced end-to-end spacing | Xi-Zong Chen, Yun-Yu Hsieh, Cha-Hsin Chao | 2019-12-24 |
| 10510598 | Self-aligned spacers and method forming same | Yi-Tsang Hsieh, Cha-Hsin Chao, Yi-Wei Chiu, Ying Ting Hsia | 2019-12-17 |
| 10510596 | Metal gates of transistors having reduced resistivity | Chia-Ching Tsai, Yi-Wei Chiu | 2019-12-17 |
| 10495970 | Critical dimension uniformity | Xi-Zong Chen, Cha-Hsin Chao, Yi-Wei Chiu, Chih-Hsuan Lin | 2019-12-03 |
| 10460995 | Method of manufacture of a FinFET device | Chia-Ching Tsai, Yi-Wei Chiu | 2019-10-29 |
| 10304729 | Method of forming interconnect structures | Chia-Ching Tsai, Yi-Wei Chiu | 2019-05-28 |
| 10290547 | Method of manufacturing a semiconductor device with metal gate etch selectivity control | Chia-Ching Tsai, Yi-Wei Chiu | 2019-05-14 |
| 10269917 | Method of forming a FinFET with work function tuning layers having stair-step increment sidewalls | Yi-Chun Chen, Tsung Fan Yin, Ying Ting Hsia, Yi-Wei Chiu | 2019-04-23 |
| 10269624 | Contact plugs and methods of forming same | Xi-Zong Chen, Y. H. Kuo, Cha-Hsin Chao, Yi-Wei Chiu | 2019-04-23 |
| 10157782 | Semiconductor device and manufacturing method thereof | Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Ying Ting Hsia | 2018-12-18 |
| 10141225 | Metal gates of transistors having reduced resistivity | Chia-Ching Tsai, Yi-Wei Chiu | 2018-11-27 |
| 10141443 | Semiconductor devices FinFET devices with optimized strained-sourece-drain recess profiles and methods of forming the same | Ying Ting Hsia, Kun-Yu Lin, Ying Wang | 2018-11-27 |
| 10083863 | Contact structure for semiconductor device | Yun-Yu Hsieh, Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Ying Ting Hsia | 2018-09-25 |
| 10074563 | Structure and formation method of interconnection structure of semiconductor device | Hua-Li Hung, Chih-Lun Lu, Hsu-Yu Huang, Tsung Fan Yin, Ying Ting Hsia +1 more | 2018-09-11 |
| 9905456 | Semiconductor device and manufacturing method thereof | Jeng Chang Her, Cha-Hsin Chao, Yi-Wei Chiu, Ying Ting Hsia | 2018-02-27 |