Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12094877 | Semiconductor device and method | Jen-Chih Hsueh, Chih-Chang Hung, Yi-Wei Chiu | 2024-09-17 |
| 12015070 | Gate structure and method of forming the same | Yi-Chun Chen, Li-Te Hsu, Ying Ting Hsia, Yi-Wei Chiu | 2024-06-18 |
| 11804488 | Semiconductor device and method | Jen-Chih Hsueh, Chih-Chang Hung, Yi-Wei Chiu | 2023-10-31 |
| 11437484 | Gate structure and method of forming the same | Yi-Chun Chen, Li-Te Hsu, Ying Ting Hsia, Yi-Wei Chiu | 2022-09-06 |
| 11398477 | Semiconductor device and method | Jen-Chih Hsueh, Chih-Chang Hung, Yi-Wei Chiu | 2022-07-26 |
| 11251079 | Method for forming semiconductor device with gate stack | Hua-Li Hung, Chih-Lun Lu, Hsu-Yu Huang, Ying Ting Hsia, Yi-Wei Chiu +1 more | 2022-02-15 |
| 11049756 | Thermal pad for etch rate uniformity | Chin-Huei Chiu, Chen-Yi Liu, Hua-Li Hung, Xi-Zong Chen, Yi-Wei Chiu | 2021-06-29 |
| 10854603 | Semiconductor device and method | Jen-Chih Hsueh, Chih-Chang Hung, Yi-Wei Chiu | 2020-12-01 |
| 10692762 | Semiconductor device with gate stack | Hua-Li Hung, Chih-Lun Lu, Hsu-Yu Huang, Ying Ting Hsia, Yi-Wei Chiu +1 more | 2020-06-23 |
| 10269917 | Method of forming a FinFET with work function tuning layers having stair-step increment sidewalls | Yi-Chun Chen, Li-Te Hsu, Ying Ting Hsia, Yi-Wei Chiu | 2019-04-23 |
| 10199252 | Thermal pad for etch rate uniformity | Chin-Huei Chiu, Chen-Yi Liu, Hua-Li Hung, Xi-Zong Chen, Yi-Wei Chiu | 2019-02-05 |
| 10074563 | Structure and formation method of interconnection structure of semiconductor device | Hua-Li Hung, Chih-Lun Lu, Hsu-Yu Huang, Ying Ting Hsia, Yi-Wei Chiu +1 more | 2018-09-11 |
| 9865697 | Semiconductor device structure and method for forming the same | Jen-Chih Hsueh, Rong-Yu Wu, Yi-Wei Chiu, Ying Ting Hsia, Li-Te Hsu | 2018-01-09 |