Issued Patents All Time
Showing 176–190 of 190 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6833578 | Method and structure improving isolation between memory cell passing gate and capacitor | Chun-Yao Chen, Huey-Chi Chu, Chung-Wei Chang, Tien-Lu Lin, Kuo-Ching Huang +3 more | 2004-12-21 |
| 6812093 | Method for fabricating memory cell structure employing contiguous gate and capacitor dielectric layer | — | 2004-11-02 |
| 6764967 | Method for forming low thermal budget sacrificial oxides | Vincent Pai, Chung-Wei Chang, Chia-Shiung Tsai, Chun-Yao Chen | 2004-07-20 |
| 6734526 | Oxidation resistant microelectronics capacitor structure with L shaped isolation spacer | Yeur-Luen Tu, Tien-Lu Lin, Chun-Yao Chen | 2004-05-11 |
| 6720232 | Method of fabricating an embedded DRAM for metal-insulator-metal (MIM) capacitor structure | Chun-Yao Chen, Huey-Chi Chu | 2004-04-13 |
| 6709919 | Method for making auto-self-aligned top electrodes for DRAM capacitors with improved capacitor-to-bit-line-contact overlay margin | — | 2004-03-23 |
| 6682982 | Process method for 1T-SRAM | Chun-Yao Chen | 2004-01-27 |
| 6642097 | Structure for capacitor-top-plate to bit-line-contact overlay margin | — | 2003-11-04 |
| 6627493 | Self-aligned method for fabricating a capacitor under bit-line (cub) dynamic random access memory (DRAM) cell structure | Chih-Hsing Yu | 2003-09-30 |
| 6602749 | Capacitor under bitline (CUB) memory cell structure with reduced parasitic capacitance | Wen-Jya Liang | 2003-08-05 |
| 6503796 | Method and structure for a top plate design for making capacitor-top-plate to bit-line-contact overlay margin | — | 2003-01-07 |
| 6486033 | SAC method for embedded DRAM devices | Wan-Yih Lieh | 2002-11-26 |
| 6300191 | Method of fabricating a capacitor under bit line structure for a dynamic random access memory device | Chih-Hsing Yu | 2001-10-09 |
| 6294426 | Method of fabricating a capacitor under bit line structure with increased capacitance without increasing the aspect ratio for a dry etched bit line contact hole | Chih-Hsing Yu | 2001-09-25 |
| 6200898 | Global planarization process for high step DRAM devices via use of HF vapor etching | — | 2001-03-13 |