Issued Patents All Time
Showing 1–25 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12433003 | 2D-channel transistor structure with asymmetric substrate contacts | Cheng-Ting Chung, Chien-Hong Chen, Mahaveer Sathaiya Dhanyakumar, Hou-Yu Chen, Kuan-Lun Cheng | 2025-09-30 |
| 12424298 | Control circuit, memory system and control method | Win-San Khwa, Jen-Chieh Liu, Meng-Fan Chang, Tung Ying Lee | 2025-09-23 |
| 12419103 | Dielectric walls for complementary field effect transistors | Cheng-Ting Chung, Yi-Bo Liao | 2025-09-16 |
| 12408387 | Transistor with a negative capacitance and a method of creating the same | Feng Yuan, Ming-Shiang Lin, Chia-Cheng Ho, Tzu-Chung Wang, Tung Ying Lee | 2025-09-02 |
| 12405736 | Operating methods, memory controllers, and memory systems | Xianwu Luo | 2025-09-02 |
| 12396235 | Semiconductor device and method for forming the same | Mahaveer Sathaiya Dhanyakumar, Cheng-Ting Chung, Chien-Hong Chen, Chung-Wei Wu | 2025-08-19 |
| 12394706 | Device with gate-to-drain via and related methods | Yi-Bo Liao | 2025-08-19 |
| 12376322 | Semiconductor device having thin bottom channel and manufacturing method thereof | Wang-Chun Huang, Hou-Yu Chen, Chih-Hao Wang | 2025-07-29 |
| 12349421 | 2D channel with self-aligned source/drain | Cheng-Ting Chung | 2025-07-01 |
| 12349409 | Semiconductor device having a gate contact on a low-k liner | Meng-Huan Jao, Huan-Chieh Su, Yi-Bo Liao, Cheng-Chi Chuang, Chih-Hao Wang | 2025-07-01 |
| 12336216 | Ferroelectric semiconductor device and method | Chia-Cheng Ho, Ming-Shiang Lin | 2025-06-17 |
| 12236100 | Operating method, memory controller, and memory system | Xianwu Luo | 2025-02-25 |
| 12191371 | Field effect transistor with disabled channels and method | Yu-Xuan Huang, Hou-Yu Chen, Zhi-Chang Lin, Chih-Hao Wang | 2025-01-07 |
| 12170323 | Nano transistors with source/drain having side contacts to 2-D material | Chao-Ching Cheng, Yi-Tse Hung, Hung-Li Chiang, Tzu-Chiang Chen, Lain-Jong Li | 2024-12-17 |
| 12009411 | Forming 3D transistors using 2D Van Der Waals materials | Sheng-Kai Su | 2024-06-11 |
| 11955527 | Nano transistors with source/drain having side contacts to 2-D material | Chao-Ching Cheng, Yi-Tse Hung, Hung-Li Chiang, Tzu-Chiang Chen, Lain-Jong Li | 2024-04-09 |
| 11930696 | Fabrication method of a double-gate carbon nanotube transistor | Sheng-Kai Su | 2024-03-12 |
| 11901004 | Memory array, memory structure and operation method of memory array | Kerem Akarvardar, Win-San Khwa, Rawan Naous, Meng-Fan Chang, Hon-Sum Philip Wong | 2024-02-13 |
| 11862243 | Memory device and method thereof | Jau-Yi Wu, Win-San Khwa, Yu-Sheng Chen | 2024-01-02 |
| 11855221 | Ferroelectric semiconductor device and method | Chia-Cheng Ho, Ming-Shiang Lin | 2023-12-26 |
| 11756645 | Control circuit, memory system and control method | Win-San Khwa, Jen-Chieh Liu, Meng-Fan Chang, Tung Ying Lee | 2023-09-12 |
| 11522085 | Ferroelectric semiconductor device and method | Chia-Cheng Ho, Ming-Shiang Lin | 2022-12-06 |
| 11489064 | Forming 3D transistors using 2D van per waals materials | Sheng-Kai Su | 2022-11-01 |
| 11443803 | Memory device and method thereof | Jau-Yi Wu, Win-San Khwa, Yu-Sheng Chen | 2022-09-13 |
| 11387360 | Transistor with a negative capacitance and a method of creating the same | Feng Yuan, Ming-Shiang Lin, Chia-Cheng Ho, Tzu-Chung Wang, Tung Ying Lee | 2022-07-12 |