Issued Patents All Time
Showing 26–50 of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11532509 | Selective hybrid capping layer for metal gates of transistors | Po-Cheng Chen, Kuo-Chan Huang, Pin-Hsuan Yeh, Wei-Chin Lee, Hsien-Ming Lee +2 more | 2022-12-20 |
| 11437280 | Semiconductor device and method of manufacture | Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Hung-Chin Chung +7 more | 2022-09-06 |
| 11430652 | Controlling threshold voltages through blocking layers | Chia-Ching Lee, Shih-Hang Chiu, Hsuan-Yu Tung, Da-Yuan Lee | 2022-08-30 |
| 11430698 | In-situ formation of metal gate modulators | Hsin-Han Tsai, Cheng-Lung Hung, Weng Chang, Chi On Chui | 2022-08-30 |
| 11404312 | Contact plug with impurity variation | Hsueh Wen Tsau, Chia-Ching Lee, Cheng-Lung Hung, Ching-Hwanq Su | 2022-08-02 |
| 11387344 | Method of manufacturing a semiconductor device having a doped work-function layer | Chia-Ching Lee, Hung-Chin Chung, Hsuan-Yu Tung, Kuan-Chang Chiu, Chien-Hao Chen +1 more | 2022-07-12 |
| 11380549 | Semiconductor device with a work function layer having a concentration of fluorine | Jung-Shiung Tsai, Wei-Fan Liao, Han-Ti Hsiaw | 2022-07-05 |
| 11322411 | Pre-deposition treatment for FET technology and devices formed thereby | Cheng-Yen Tsai, Tai-Wei Hwang, Hung-Chin Chung, Wei-Chin Lee, Da-Yuan Lee +3 more | 2022-05-03 |
| 11302818 | Gate resistance reduction through low-resistivity conductive layer | Po-Cheng Chen, Kuo-Chan Huang, Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen | 2022-04-12 |
| 11302582 | Pre-deposition treatment for FET technology and devices formed thereby | Cheng-Yen Tsai, Tai-Wei Hwang, Hung-Chin Chung, Wei-Chin Lee, Da-Yuan Lee +3 more | 2022-04-12 |
| 11289480 | Semiconductor device and method | Shih-Hang Chiu, Chih-Chang Hung, I-Wei Yang, Shu-Yuan Ku, Cheng-Lung Hung +2 more | 2022-03-29 |
| 11127836 | Metal gate scheme for device and methods of forming | Chia-Ching Lee, Da-Yuan Lee, Hsueh Wen Tsau | 2021-09-21 |
| 11094828 | Geometry for threshold voltage tuning on semiconductor device | Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai +3 more | 2021-08-17 |
| 11075275 | Metal gate fill for short-channel and long-channel semiconductor devices | Shih-Hang Chiu, Ching-Hwanq Su, Da-Yuan Lee, Ji-Cheng Chen, Kuan-Ting Liu +2 more | 2021-07-27 |
| 11056395 | Transistor metal gate and method of manufacture | Hung-Chin Chung, Hsien-Ming Lee, Chien-Hao Chen, Ching-Hwanq Su | 2021-07-06 |
| 10867864 | Semiconductor device and method of manufacture | Hsin-Han Tsai, Wei-Chin Lee, Chia-Ching Lee, Hung-Chin Chung, Cheng-Lung Hung +1 more | 2020-12-15 |
| 10867848 | Semiconductor device and method | Hsueh Wen Tsau, Chia-Ching Lee, Cheng-Lung Hung, Ching-Hwanq Su | 2020-12-15 |
| 10847637 | Semiconductor device and method | Shih-Hang Chiu, Chia-Ching Lee, Da-Yuan Lee, Ching-Hwanq Su | 2020-11-24 |
| 10833196 | FinFET structures and methods of forming the same | Yu-Sheng Wang, Chi-Cheng Hung, Chia-Ching Lee, Ching-Hwanq Su | 2020-11-10 |
| 10756087 | Semiconductor device and method | Shih-Hang Chiu, Chih-Chang Hung, I-Wei Yang, Shu-Yuan Ku, Cheng-Lung Hung +2 more | 2020-08-25 |
| 10741400 | Gate replacement structures in semiconductor devices | Hsueh Wen Tsau, Chia-Ching Lee, Da-Yuan Lee | 2020-08-11 |
| 10727066 | Semiconductor device and methods of manufacture | Jung-Shiung Tsai, Wei-Fan Liao, Han-Ti Hsiaw | 2020-07-28 |
| 10692770 | Geometry for threshold voltage tuning on semiconductor device | Wei-Chin Lee, Shih-Hang Chiu, Chia-Ching Lee, Hsueh Wen Tsau, Cheng-Yen Tsai +3 more | 2020-06-23 |
| 10504789 | Pre-deposition treatment for FET technology and devices formed thereby | Cheng-Yen Tsai, Tai-Wei Hwang, Hung-Chin Chung, Wei-Chin Lee, Da-Yuan Lee +3 more | 2019-12-10 |
| 10504734 | Semiconductor device and methods of manufacture | Jung-Shiung Tsai, Wei-Fan Liao, Han-Ti Hsiaw | 2019-12-10 |